Srijan: A Methodology for Synthesis of ASIP Based Multiprocessor SoCs Project Overview Presentation

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Srijan A Methodology for Synthesis of ASIP Based
Multiprocessor SoCs Project Overview
Presentation

• Anshul Kumar

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Outline

• ASSET and ASSIST contributions
• Why customize architectures?
• Customization opportunities in multiprocessors
• Customization opportunities in VLIW ASIPs
• Synthesis flow in Srijan
• Discussions about various projects, scope, goals
  etc.
• Conclusion

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ASSET and ASSIST Historical Perspective

• 1998-1999
• Embedded systems activity starts at IIT Delhi
• Initial definition of ASSET methodology and
  exposure to SUIF
• 1999-2000
• ASIP related (ASSIST) activity starts at IIT
  Delhi
• First version of tools for, H/W and S/W
  estimation and paritioning
• Kernel and Interface synthesis related activity
  starts
• 2000-2001
• LEON and Trimaran related activities starts
• Various co-design case studies and integration of
  various tools
• 2001-2002
• Exploration of register file size and register
  windows in ASIP synthesis
• Framework for evaluation of special Fus in VLIW
  ASIPs
• Hardware synthesizer with automatic interface
  generation for LEON
• Evaluating Scratchpad memory as an alternative to
  on-chip cache

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ASSET Objectives and Contributions

• Objectives
• Define a methodology to automatically synthesize
  real-time compute intensive embedded systems and
  develop supporting tools
• Contributions
• Methodology for automatic synthesis of compute
  intensive embedded systems has been defined
• hardware software Estimation -gt partitioning -gt
  synthesis -gt validation
• Supporting tools have been developed for
• hardware estimation
• software estimation
• partitioning of the application
• Synthesis hardware, software, interface and
  real time kernel
• Funding Agency
• Naval Research Board, Govt. of India
• Duration 1998 - 2002

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ASSIST Objectives and Contributions

• Objectives
• Develop a methodology to explore design space of
  Application Specific Instruction Processors
  (ASIPs)
• Contributions
• Methodology for ASIP design space exploration has
  been defined which consists of
• register file exploration
• custom FU evaluation
• Evaluation of scratchpad as an alternative to
  cache
• Funding Agency
• DST-DAAD Joint Research Program, Govt. of India
  and Govt. of Germany
• Duration 2000 - 2003

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Why Application Specific Multiprocessors ?

• Higher performance
• Lesser area
• Low power

Compute Intensive Application

• Lower Cost

Control Part
General Purpose Multiprocessor
Application Specific Multiprocessor
No customization
Customization
Higher Performance
Avg. Performance
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Role of Processor Customization

• Allows effective utilization of resources
• Makes solution cheaper

Requires operation on pixel value of the range
0-255
Processor1 with 32 bit datapath
Processor2 with 8 bit datapath
Cheaper Solution
Costly Solution
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Customization Opportunities -gt System Level

• Compute units
• No. and Types ASICs, VLIW or RISC ASIPs, DSPs
• Interconnection Network
• Shared bus, MINs or crossbar switches
• Custom interconnection based on communication
  pattern of the application
• Memory architecture
• Types synchronous/asynchronous,
  pipelined/non-pipelined etc.
• Various transfer modes
• Custom memories FIFOs, frame buffers etc.

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Customization Opportunities -gt System Level
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Customization Opportunities -gt Processor Level

• Functional Units
• MISO, MIMO, MIMO with LD/ST
• Rigid or flexible I/O timeshapes
• Register File Clustering
• Each FU can read from and write to only a subset
  of registers
• Area grows as N3, Delay grows as N3/2, Power
  grows as N3
• where N is the no. of Functional Units connected
  to the register file
• Powerful application analysis required to
  minimize data copying
• Interconnects
• between different clusters and between clusters
  and memory
• Analysis of data access patterns required for
  evaluating cost-performance tradeoffs
• Current ASIP vendors do not offer customizable
  interconnects
• Instruction encoding and decoding
• Reduce or remove explicit NOPs in code
• Affects Code size, Object code compatibility,
  Branch miss prediction penalty, Hardware cost,
  Address specification in code size

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Customization Opportunities -gt Processor Level
Register Files
RF1
RF2
No. and Type of Regfile Customization
Interconnect Customization
Functional Units
FU1
FU2
FU3
FU4
AFU2
AFU1
No. and Type of FU Customization
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Overall Methodology
Executable Application Specification
Architecture Description
System-level Exploration
Subsystem-level Exploration
Refined Arch. Description
Estimates Match Simulation Results?
Task-set and Constraints
No Changes
Yes
Validation Framework
Refine Methodo./Est. Algos.
No
Chg Arch. Desc., Constr. etc.
Yes
Constraints Met?
O/p to Synthesizer
Constraints
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Projects -gt ASIP Simulator

• Objective
• Develop a parameterized cycle true simulator
  using SystemC
• Input
• Encoded instructions or object code
• Output
• Performance statistics and trace
• Validation
• Model TriMedia and ARM and compare results with
  their cycle true proprietary simulators

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Projects -gt Compiler Backend

• Objective
• To develop a compiler backend using the IMPACT
  framework for a clustered VLIW architecture
• Input
• C application code along with MDES reflecting
  target processor
• Output
• Assembly code and simulation statistics (from
  IMPACT simulator)
• Validation
• Model TriMedia and compare results against their
  proprietary compiler. Also model a hypothetical
  clustered ASIP and compare with manually
  generated code

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Projects -gt Multiprocessor Prototype

• Objective
• Extend LEON processor for shared memory
  multiprocessor type of configuration. Finally
  download and test using ADM-XRC board. Port RTEMS
  shared memory driver to this multiprocessor
  configuration.
• Input
• NA
• Output
• NA
• Validation
• Initially validate against some small programs
  directly put into ROM. Later on show a complete
  application running on RTEMSMultiprocessor LEON
  configuration

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Projects -gt Power Models in Trimaran/IMPACT

• Objective
• To extend IMPACT/Trimaran duo for generating
  power consumption information using power models.
• Input
• Power parameters and execution trace
• Output
• Power statistics for the application and
  processing elements
• Validation
• Validate against ARM processor and TriMedia

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Projects -gt Coproc and FU Evaluation

• Objective
• To establish a link between ASSET and Trimaran
  related activity by performing case studies using
  tools developed under ASSET. Also, fine tune the
  frameworks in case the results are different.
• Input
• Application and parameters
• Output
• Performance statistics
• Validation
• Validate against estimators and results obtained
  after actual synthesis/simulation

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Projects -gt Encoding Framework

• Objective
• To define a new encoding specification language
  supporting easy representation of VLIW
  instructions
• Input
• Assembly code and encoding scheme
• Output
• Object code
• Validation
• Model encoding schemes in TriMedia and Ti C6x and
  compare with their proprietary tool sets.

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Projects -gt Memory Optimization in H/W Synthesizer

• Objectives
• Write a C-to-VHDL compiler to support larger
  subset of C
• global memory accesses
• nested function calls
• Apply memory optimizations such as
• local memory pool
• effective use of fast memory access modes etc.
• Inputs
• Application IR
• Names of the functions to be converted to VHDL
• Outputs
• VHDL for hardware mapped functions along-with
  hardware and software interfaces

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Projects -gt Pipelined Coproc Generation

• Objectives
• Incorporate data and functional parallelism in
  C-to-VHDL compiler
• Explore possibility of pipelining in generated
  VHDL of the function
• Inputs
• Application IR
• Names of the hardware mapped functions
• Outputs
• VHDL for hardware mapped functions along-with
  hardware and software interfaces

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Projects -gt S/W Estimation for Multiprocessors

• Objectives
• Define multiprocessor architecture description
• Develop a tool to generate annotated task graph
  with information such as
• Estimates for data communication
• Estimates for synchronization overhead
• Inputs
• Application IR
• Profile data
• Architecture description
• Outputs
• Annotated task graph

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Projects -gt Arch. Model Gen. using SystemC

• Objectives
• Make the simulator generator retargetable using
  architecture description
• Refine component libraries
• Inputs
• Application IR
• Architecture description
• Outputs
• SystemC models of the architecture using
  simulator generator

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Projects -gt Application Modeling

• Objectives
• Create multithreaded implementation of given
  vision applications
• Study the application from architecture point of
  view. Analysis
• Bitwidths
• Data communication
• Memory accesses etc.
• Inputs
• Sequential vision applications
• Outputs
• Multithreaded implementation of these
  applications and their characteristics

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Conclusion
Srijan Starts...
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Thanks
Thanks