Fundamentals%20of%20Digital%20Signal%20Processing

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Fundamentals of Digital Signal Processing
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What is DSP?

• Converting a continuously changing waveform
  (analog) into a series of discrete levels
  (digital) and then performing Digital Computations

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What is DSP?

• The analog waveform is sliced into equal segments
  and the waveform amplitude is measured in the
  middle of each segment
• The collection of measurements make up the
  digital representation of the waveform

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A/D Parameters

• 1. Sampling Frequency The rate at which we
  convert the analog data into digital
• 2. Dynamic range The ratio between the highest
  to lowest value (which is not zero)

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What is DSP?
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Converting Analog into DigitalElectronically

• The device that does the conversion is called an
  Analog to Digital Converter (ADC)
• There is a device that converts digital to analog
  that is called a Digital to Analog Converter (DAC)

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Converting Digital to Analog Electronically

• The simplest form of DAC uses a resistance ladder
  where the different bits close a gate enabling
  more current to flow through the resistors and
  create the corresponding analog voltage.

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Converting Analog into DigitalElectronically

• The output of the resistance ladder is compared
  to the analog voltage in a comparator
• When there is a match, the digital equivalent
  (switch configuration) is captured

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Analog to Digital (Ladder Comparison)
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Converting Analog into DigitalComputationally

• The binary search is a mathematical technique
  that uses an initial guess, the expected high,
  and the expected low in a simple computation to
  refine a new guess
• The computation continues until the refined guess
  matches the actual value (or until the maximum
  number of calculations is reached)
• Faster way, start with previous value as the
  initial guess

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First Pacemaker 1957
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Pacemaker / Defribliator
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Congestive Heart Failure Detector
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VHDL A QUICK PRIMER
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Lets Start Simple

• Support different description levels
• Structural (specifying interconnections of the
  gates),
• Dataflow (specifying logic equations), and
• Behavioral (specifying behavior)

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VHDL Description of Combinational Networks
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Entity-Architecture Pair
port names
port mode (direction)
entity name
punctuation
port type
reserved words
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VHDL Program Structure
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4-bit Adder
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4-bit Adder (contd)
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4-bit Adder - Simulation
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Modeling Flip-Flops Using VHDL Processes

• Whenever one of the signals in the sensitivity
  list changes, the sequential statements are
  executed in sequence one time

General form of process
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D Flip-flop Model
Bit values are enclosed in single quotes
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JK Flip-Flop Model
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JK Flip-Flop Model
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Using Nested IFs and ELSEIFs
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VHDL Models for a MUX
Sel represents the integerequivalent of a 2-bit
binary number with bits A and B
If a MUX model is used inside a process, the MUX
can be modeled using a CASE statement(cannot use
a concurrent statement)
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MUX Models (1)

• architecture RTL1 of SELECTOR is
• begin
• p0 process (A, SEL)
• begin
• if (SEL "0000") then Y lt A(0)
• elsif (SEL "0001") then Y lt A(1)
• elsif (SEL "0010") then Y lt A(2)
• elsif (SEL "0011") then Y lt A(3)
• elsif (SEL "0100") then Y lt A(4)
• elsif (SEL "0101") then Y lt A(5)
• elsif (SEL "0110") then Y lt A(6)
• elsif (SEL "0111") then Y lt A(7)
• elsif (SEL "1000") then Y lt A(8)
• elsif (SEL "1001") then Y lt A(9)
• elsif (SEL "1010") then Y lt A(10)
• elsif (SEL "1011") then Y lt A(11)
• elsif (SEL "1100") then Y lt A(12)
• elsif (SEL "1101") then Y lt A(13)
• elsif (SEL "1110") then Y lt A(14)

• library IEEE
• use IEEE.std_logic_1164.all
• use IEEE.std_logic_unsigned.all
• entity SELECTOR is
• port (
• A in std_logic_vector(15 downto 0)
• SEL in std_logic_vector( 3 downto 0)
• Y out std_logic)
• end SELECTOR

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MUX Models (2)

• architecture RTL3 of SELECTOR is
• begin
• with SEL select
• Y lt A(0) when "0000",
• A(1) when "0001",
• A(2) when "0010",
• A(3) when "0011",
• A(4) when "0100",
• A(5) when "0101",
• A(6) when "0110",
• A(7) when "0111",
• A(8) when "1000",
• A(9) when "1001",
• A(10) when "1010",
• A(11) when "1011",
• A(12) when "1100",
• A(13) when "1101",
• A(14) when "1110",
• A(15) when others

• library IEEE
• use IEEE.std_logic_1164.all
• use IEEE.std_logic_unsigned.all
• entity SELECTOR is
• port (
• A in std_logic_vector(15 downto 0)
• SEL in std_logic_vector( 3 downto 0)
• Y out std_logic)
• end SELECTOR

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MUX Models (3)

• architecture RTL2 of SELECTOR is
• begin
• p1 process (A, SEL)
• begin
• case SEL is
• when "0000" gt Y lt A(0)
• when "0001" gt Y lt A(1)
• when "0010" gt Y lt A(2)
• when "0011" gt Y lt A(3)
• when "0100" gt Y lt A(4)
• when "0101" gt Y lt A(5)
• when "0110" gt Y lt A(6)
• when "0111" gt Y lt A(7)
• when "1000" gt Y lt A(8)
• when "1001" gt Y lt A(9)
• when "1010" gt Y lt A(10)
• when "1011" gt Y lt A(11)
• when "1100" gt Y lt A(12)
• when "1101" gt Y lt A(13)

• library IEEE
• use IEEE.std_logic_1164.all
• use IEEE.std_logic_unsigned.all
• entity SELECTOR is
• port (
• A in std_logic_vector(15 downto 0)
• SEL in std_logic_vector( 3 downto 0)
• Y out std_logic)
• end SELECTOR

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MUX Models (4)

• library IEEE
• use IEEE.std_logic_1164.all
• use IEEE.std_logic_unsigned.all
• entity SELECTOR is
• port (
• A in std_logic_vector(15 downto 0)
• SEL in std_logic_vector( 3 downto 0)
• Y out std_logic)
• end SELECTOR

• architecture RTL4 of SELECTOR is
• begin
• Y lt A(conv_integer(SEL))
• end RTL4

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Moore FSM

• Output depends ONLY on current state
• Outputs associated with each state are set at
  clock transition

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Mealy FSM

• Output depends on inputs AND current state
• Outputs are set during transitions

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Coding FSMs in Altera
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Process Statement

• Process computes outputs of sequential statements
  on each clock tick with respect to the sensitive
  signals.

Sensitivity list
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EVENT

• EVENT is an Altera construct that represents
  when the signal is transitioning

IF statement readsIf Clock is making a positive
transition THEN
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VHDL codes for FSM

• Mealy FSM see mealy1.vhd on the web
• Moore FSM - see moore.vhd on the web
• Now lets take a look how to edit, compile,
  simulate and synthesize your design using Altera
  software .
• . (proceed with hands on tutorial)

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FSMs in VHDL

• Finite State Machines Can Be Easily Described
  With Processes
• Synthesis Tools Understand FSM Description If
  Certain Rules Are Followed
• State transitions should be described in a
  process sensitive to clock and asynchronous reset
  signals only
• Outputs described as concurrent statements
  outside the process

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FSM States (1)
architecture behavior of FSM is type state
is (list of states) signal FSM_state
state begin process(clk, reset)
begin if reset 1 then
FSM_state lt initial state
else case FSM_state is
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FSM States (2)
case FSM_state is when state_1
gt if transition condition 1
then FSM_state lt
state_1 end if
when state_2 gt if transition
condition 2 then FSM_state
lt state_2 end if end
case end if end process
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Moore FSM - Example 1

• Moore FSM that Recognizes Sequence 10

reset
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Moore FSM in VHDL
type state is (S0, S1, S2) signal Moore_state
state U_Moore process(clock,
reset) Begin if(reset 1) then Moore_state
lt S0 elsif (clock 1 and clockevent)
then case Moore_state is when S0 gt if
input 1 then Moore_state lt S1 end
if when S1 gt if input 0 then
Moore_state lt S2 end if when S2 gt if
input 0 then Moore_state lt S0 else
Moore_state lt S1 end if end case end
if End process Output lt 1 when Moore_state
S2 else 0
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Mealy FSM - Example 1

• Mealy FSM that Recognizes Sequence 10

0 / 0
1 / 0
1 / 0
S0
S1
reset
0 / 1
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Mealy FSM in VHDL
type state is (S0, S1) signal Mealy_state
state U_Mealy process(clock,
reset) Begin if(reset 1) then Mealy_state
lt S0 elsif (clock 1 and clockevent)
then case Mealy_state is when S0 gt if
input 1 then Mealy_state lt S1 end
if when S1 gt if input 0 then
Mealy_state lt S0 end if end case end
if End process Output lt 1 when (Mealy_state
S1 and input 0) else 0
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Moore FSM Example 2 State diagram
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Moore FSM Example 2 State table
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Moore FSM
Transition function
Input w
Next State
Present State y
Memory (register)
Output function
Output z
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Moore FSM Example 2 VHDL code (1)
USE ieee.std_logic_1164.all ENTITY simple
IS PORT ( Clock, Resetn, w IN STD_LOGIC
z OUT STD_LOGIC ) END simple
ARCHITECTURE Behavior OF simple IS TYPE
State_type IS (A, B, C) SIGNAL y State_type
BEGIN PROCESS ( Resetn, Clock ) BEGIN IF
Resetn '0' THEN y lt A ELSIF
(Clock'EVENT AND Clock '1') THEN cont ...
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Moore FSM Example 2 VHDL code (2)
CASE y IS WHEN A gt IF w '0' THEN
y lt A ELSE y lt B
END IF WHEN B gt IF w '0'
THEN y lt A ELSE y lt C
END IF WHEN C gt IF w '0'
THEN y lt A ELSE y lt C
END IF END CASE END IF END
PROCESS z lt '1' WHEN y C ELSE '0' END
Behavior
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Moore FSM
Transition function
Input w
Next State y_next
Present State y_present
Memory (register)
Output function
Output z
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Alternative VHDL code (1)
ARCHITECTURE Behavior OF simple IS TYPE
State_type IS (A, B, C) SIGNAL y_present,
y_next State_type BEGIN PROCESS ( w,
y_present ) BEGIN CASE y_present IS WHEN A
gt IF w '0' THEN y_next lt A
ELSE y_next lt B END IF
WHEN B gt IF w '0' THEN y_next lt
A ELSE y_next lt C END IF
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Alternative VHDL code (2)
WHEN C gt IF w '0' THEN y_next lt A
ELSE y_next lt C END IF END
CASE END PROCESS PROCESS (Clock,
Resetn) BEGIN IF Resetn '0'
THEN y_present lt A ELSIF (Clock'EVENT AND
Clock '1') THEN y_present lt y_next END
IF END PROCESS z lt '1' WHEN y_present C
ELSE '0' END Behavior
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Mealy FSM Example 2 State diagram
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Mealy FSM Example 2 State table
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Mealy FSM
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Mealy FSM Example 2 VHDL code (1)
LIBRARY ieee USE ieee.std_logic_1164.all
ENTITY mealy IS PORT ( Clock, Resetn, w
IN STD_LOGIC z OUT STD_LOGIC ) END
mealy ARCHITECTURE Behavior OF mealy IS TYPE
State_type IS (A, B) SIGNAL y State_type
BEGIN PROCESS ( Resetn, Clock ) BEGIN IF
Resetn '0' THEN y lt A ELSIF
(Clock'EVENT AND Clock '1') THEN CASE y
IS WHEN A gt IF w '0' THEN y lt A
ELSE y lt B END IF
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Mealy FSM Example 2 VHDL code (2)
WHEN B gt IF w '0' THEN y lt A
ELSE y lt B END IF END CASE
END IF END PROCESS with y select z
lt w when B, z lt 0 when
others END Behavior
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Compilation and Simulation of VHDL Code

• Compiler (Analyzer) checks the VHDL source code
  
• does it conforms with VHDL syntax and semantic
  rules
• are references to libraries correct
• Intermediate form used by a simulator or by a
  synthesizer
• Elaboration
• create ports, allocate memory storage, create
  interconnections, ...
• establish mechanism for executing of VHDL
  processes