SEMICONDUCTOR MEMORIES

1
SEMICONDUCTOR MEMORIES
2
Chapter Overview
3
Semiconductor Memory Classification
4
Memory Architecture Decoders
5
Array-Structured Memory Architecture
6
Hierarchical Memory Architecture
7
MOS NOR ROM Layout
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MOS NOR ROM Layout
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MOS NAND ROM
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MOS NAND ROM Layout
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Precharged MOS NOR ROM
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Characteristics of State-of-the-art NVM
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Read-Write Memories (RAM)
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6-transistor CMOS SRAM Cell
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CMOS SRAM Analysis (Write)
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CMOS SRAM Analysis (Read)
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6T-SRAM Layout
VDD
M4
M2
Q
Q
M1
M3
GND
WL
M5
M6
BL
BL
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Resistance-load SRAM Cell
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3-Transistor DRAM Cell
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3T-DRAM Layout
BL2
BL1
GND
RWL
M3
M2
WWL
M1
21
1-Transistor DRAM Cell
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DRAM Cell Observations
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1-T DRAM Cell
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Periphery
25
Row Decoders
Collection of 2M complex logic gates Organized in
regular and dense fashion
(N)AND Decoder
NOR Decoder
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Dynamic Decoders
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A NAND decoder using 2-input pre-decoders
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4 input pass-transistor based column decoder
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4-to-1 tree based column decoder
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Sense Amplifiers
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Differential Sensing - SRAM
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Latch-Based Sense Amplifier
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Open bitline architecture
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DRAM Read Process with Dummy Cell
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Programmable Logic Array
36
Pseudo-Static PLA
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Dynamic PLA
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Clock Signal Generation for self-timed dynamic
PLA
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PLA Layout
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PLA versus ROM
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Semiconductor Memory Trends
Memory Size as a function of time x 4 every
three years
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Semiconductor Memory Trends
Increasing die size factor 1.5 per
generation Combined with reducing cell size
factor 2.6 per generation
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Semiconductor Memory Trends
Technology feature size for different SRAM
generations