TFT(Thin Film Transistor)

1
TFT(Thin Film Transistor)
Compensated Back-Channel TFTs in Hydrogenated
Amorphous Silicon
J. M. Shannon and E. G. Gerstner
IEEE Electron device letters, vol. 24, no. 1,
january 2003
In cheol, Nam _at_ S!LK
2
Introduction(1)

• In the early 1960s

High surface state densities
Poorly characterized polycrystalline II-VI
compound films evaporated insulators

• In the 1975, W.E. Spear P. G. LeComber

With process parameter optimization ( RF Glow
Discharge Method )
Hydrogenated Amorphous Silicon(a-SiH)

• Large-area integration, Low cost, High photo
  sensitive
• ? Solar cell, Image sensor, LCD

3
Introduction(2)

• Limits the ultimate speed of devices

• Low Electron Mobility

• High photo sensitive ? Photo-leakage current

• Advantages of Hydrogenated Amorphous Silicon

• Low temperature deposition fabrication
  processes

• Low cost glass substrate

• Low interface states with SiNx

• Capability of being deposited on a large area

• Low leakage current

4
Hydrogenated Amorphous Silicon?(1)

• Single Crystal

• Diamond Structure
• Constant Ec, Ev, Eg
• Low Trap Density

• Fast Mobility
• Doping possibility
• High Temperature

• Amorphous

• ??? ??
• Band-Tail States
• High Density of
• Dangling Bond(?????)
• ? Trap (Localized States)

5
Hydrogenated Amorphous Silicon?(2)

• Band-Tail

6
Hydrogenated Amorphous Silicon?(3)

• A-SiH

• Hydrogen content 1030
• PECVD(Plasma Enhanced
• Chemical Vapor Deposition)

SiH4
SiH4 NH3
Substrate lt 350?
A-SiH
SiNx
7
A-SiH Deposition Method

• Plasma Enhanced Chemical Vapor Deposition(PECVD)

• Low Plasma Density 1010cm-3

• Capacitive Coupled Plasma(CCP)

• High Plasma Density 1012cm-3

• High Density
• High Etch rate

• Helicon Wave Plasma

• Inductively-Coupled Plasma(ICP)

• Electron Cyclotron Resonance(ECR) Plasma

• Low pressure etching
• With input microwave power 100W2kW
• In scaling to larger ( gt200 nm)

Ex) Conventional ECR 2.45GHz, 875G(Magnetized
electrons gt 100eV) ? Damage
8
Hydrogenated Amorphous Silicon?(4)

• A-SiH

• Hydrogenated Amorphous Silicon?? trapping(a)?
  hopping(b)? ?? ??? ?? ??

9
Hydrogenated Amorphous Silicon?(5)

• Property

10
TFT Structure(1)

• Conventional Structure of A-SiH TFTs

G
S
D
D
S
G
G
S
D
S
D
G

• Staggered Source/Drain Gate ? The Opposite
  Side

• Coplanar Source/Drain Gate ? The Same Side

11
TFT Structure(2)

• Back-channel inverted staggered TFT

• Easier to obtain a good
• device when the dielectric
• is deposited first

• The first a-SiH TFT
• by LeComber et al.
• Still being used widely
• in TFT-LCD

• Must be minimized parasitic
• Current via Two Layer
• na-SiH a-SiH

12
TFT Structure(3)

• To reduce parasitic resistance
• To fabricate large area display

Issue
Problem 1

• Gate-line RC-delay in bottom gate TFT structure

• Top gate TFT structure (normal staggered
  coplanar)

Problem 2

• Uniform fabrication of small TFT in a large area
  substrate

• Self-alignment processed TFT

Problem 3

• How to reduce the noise ?

• To optimize the pixel arrangement and the size
  of self-aligned TFT

13
TFT Structure(4)

• Self-aligned process

• Require a long rear exposure to the resist
  through the glass substrate

• Advantage

? Large-area doping ? Simple fabrication
process ? No need of n deposition chamber
? Ion implantation using the gate as a mask

• Problem of conventional self-aligned process

? Cause damage in the material
Coplanar Etch Stopper
? Annealing(Tmaxlt 300?)
? All damage cannot be removed
? High resistance source/drain contact
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TFT Structure(5)

• Etch Stopper

• Plasma treatment

SiNx
15
Compensated Back-Channel TFTs in A-SiH(1)

• Abstract

• Ion Implantation Process

To compensate the channel region
Good source drain ohmic contact
Donor impurity
Acceptor impurity
Compensation
16
Compensated Back-Channel TFTs in A-SiH(2)
I. Introduction

• Two mainstream technology for Inverted staggered
  TFT in A-SiH

Back Channel
Etch Stopper
SiNx
17
Compensated Back-Channel TFTs in A-SiH(3)

• Problem

• Variation of back-channel etch depth
• of thickness of the n layer

• Difficult to consistently obtain low off-current
• to remove all the n layer

• Solution

• Compensation (donor acceptor)
• Ion implantation
• (to obtain good matching between donor and
  accepter in a-SiH)
• but, some residual disorder after annealing
  activating
• ? Damage !

18
Compensated Back-Channel TFTs in A-SiH(4)
II. Sample Preparation
10KeV

• Mo Gate electrode
• Glass Substrate
• 300nm SiNx
• 150nm a-SiH
• 300? PECVD
• P31 2 X 1015cm-2
• Cr Source/Drain
• BF492 12KeV, 13KeV, 14KeV
• Annealing 250? for 30min in N2

19
Compensated Back-Channel TFTs in A-SiH(5)
Ref5. S.Laun et al, An experimental study of
the source/drain parasitic resistance effects in
a-SiH TFT, J. Appl. Phys, vol. 17, pp.766-772,
1992
III. Results and Discussion

• The peak concentration of P 1 X 1021cm-2
• located 17nm below contact

Within a factor 2 of Self-aligned method
Channel Resistance
Fig. 2. Width-normalized on-resistance against
channel length for different gate voltages. 210
cm 10-keV P source and drain implant.
20
Compensated Back-Channel TFTs in A-SiH(6)

• Best match of computer calculation BF2 12KeV
• At 12Kev, penetrate 150nm a-SiH
• ? Damage ! ( more 13KeV gt 12KeV )
• Same Dimension, Similar shape, No significant VT
• Dopant, Damage center have negligible effect.
• Do not affect electron mobility
• with the back channel compensation technique

Due to contact resistanceRef.7
High energy Damage
21
Compensated Back-Channel TFTs in A-SiH(7)

• Leakage Current Matching

• Experiment

• Different Energy Dose of BF2
• 600µm Width
• Off current lt 1 pA
• Excellent value more
• than the best TFT with
• n deposited contact

• Need a much lower dose
• ? because of residual damage

Will increase density of states in The a-SiH
band gap
22
Compensated Back-Channel TFTs in A-SiH(8)
IV. Conclusion

• Inverted staggered TFT have been made in a-SiH
• using back-channel compensation.
• To give good S/D contact, P 1 X 1021cm-3
• ? Be possible to compensate in the
  back-channel region using BF2
• To be made with low source-drain leakage current
• ? Lower dose ( lt 1 X 1015cm-3 13KeV BF2 )

23
Appendix

• Review of self-aligned TFTs in A-SiH

• Advantage of the transparency of glass substrate
• The patterned gates act as a photomask.
• In the rear exposure process
• Source/Drain contact can be self-aligned using a
  lift-off
• ? The overlap between gate and S/D ? Be small
  !!
• ? An overlap length of 1-2µm is necessary.
• To control the overlap accurately !!

24
Method of Kodama et. Al. (Fujitsu) reported
???Glass ? NiCr ? SiO2 ? a-Si ? PR ? Al ? a-Si ?
SiO2 ???
Patterned
Patterned
illumination
Deposition
Coated
Lift-off
Light-shielding
SiNx
25
Method of Chenevas-Paule et al. (LETI) reported
???Glass ? Gate ? SiO2 ? a-SiH ? SiO2 ? PR ? n
a-SiH ? Cr ???
Patterned
Deposition
Deposition
Coated
illumination
Lift-off
26
Method of Busta et al. (Amoco) reported
???Glass ? NiCr ? SiNx ? a-Si ? n a-SiH ? PR ?
NiCr ???
Patterned
Deposition
Deposition
Coated
illumination
Lift-off

• Using photoresist stripper

27
Method of Akiyama et al. (Toshiba) reported
??Glass ? MoTa ? SiO2 ? SiNx ? a-SiH ? SiNx ? PR
? na-SiH ? Al/Cr ??
Patterned
Deposition
Coated
illumination

• A top SiNx insulator
• to passivate the rear interface and to
  protect the thin intrinsic layer
• from process damage during n-layer etching

28
Method of Hirano et al. (NEC) reported
???Glass ? Gate ? SiNx ? a-SiH ? SiNx ? PR ?
na-SiH ? S/D ???
Ion Implantation
Coated
illumination
na-SiH
29
Method of Akiyama et al. (Toshiba) reported
??Glass ? Gate ? SiNx ? a-Si ? SiNx ? PR ?
na-SiH ? Mo ? Al/Cr ??
Ion implantation
Mo-Si reaction (Mo-Silicide layer)
PHx
Reduce resistance of the electric lead which
connects between S/D electrodes and a channel
region.
30
Method of Kakkad et al. (Toshiba) reported
???Glass ? Gate ? Insulator ? a-Si ? Poly-Si(n) ?
ITO ? Mo ? SiNx ???
Deposition
Passivation
Deposition
Spin-Coated(SOG)
Patterned
Laser annealing

• ITO-Mo double layer
• To reduce the signal-line resistance

31
Method of Kuo reported
In order to reduce the Photo-Leakage Current
under light illumination
to increase On Current

• Two Gate Bottom Top
• Same area as conventional single-channel TFT
• Light from either top or bottom of Transistor
  cannot
• reach the channel

32
Method of Kuo (Split-Gate) reported
???To increase on-current To reduce the area
accupancy ???

• Two interconnected sub-TFTs that share the S/D
  and Gate
• The width can be as narrow as 0.5 µm

33
Method of Jackson et al. reported
With deposited doped contact layer using two back
side exposure and lift-off method

• Channel definition requiring no precise contact
  alignment
• SiNx is patterned by a backside exposure step
• n contact layer is deposited
• contact area are defined by 2nd backside
  exposure step
• The data-line metal is deposited and lifted off
• n regions are removed by reactive ion etching

34
Ref5. S.Laun et al, An experimental study of
the source/drain parasitic resistance effects in
a-SiH TFT, J. Appl. Phys, vol. 17,pp.766-772,
1992
Threshold Voltage 5.32V
35
Ref7. C.-D. Kim et al, Short-channel
amorphous silicon thin-film devices, IEEE Trans.
Electron Devices, vol. 43, pp.2172-2176, Dec. 1996

• Since the flat n poly-Si region has
  satisfactorily dense electrons and low
  resistivity

• This result cannot be interpreted by the
  conventional parasitic resistances.

• But means that there was another large parasitic
  resistance in the TFTs

• Analysis Schematic view of the thick gate TFT

• SiNx a-Si surfaces take a cylindrical form

• The Si region near the side-wall having a thick
  vertical size

• Cannot be crystallized well

• By excimer-laser light
• ? Sometimes remains in an amorphous state