a fabless design house developing patented SiFET technologies for ultrahigh efficiency, lowpower ele

1

• a fabless design house developing patented SiFET
  technologies for ultra-high efficiency, low-power
  electronics

2
The Problem
Low dropout regulators (LDOs) are used in almost
all portable electronics to ensure constant
supply voltage as the battery voltage falls with
time
The LDO chip itself uses some voltage of its
own(called the dropout voltage) The higher the
dropout voltage the lower the efficiency, and the
shorter the battery lifetime.Existing LDO chips
have dropout voltages gt50 mV and require
additional componentse.g. to ensure stable
operation
3
Our Solution
Our patented Si-FET technology has several key
advantages

• ultra-low dropout voltages (lt20 mV) ? higher
  efficiency, longer battery lifetime
• requires fewer external components ? reduced
  volume, reduced cost, increased reliability
• Si-FET technology is robust and suitable for
  aerospace industry
• similar parts will be developed for the
  high-volume/low-margins commercial sector as well
  as the low-volume/high-margins aerospace industry

4
The Opportunity
The LDO market is growing and is not dominated by
a single manufacturer
5
The Company

• SJT Micropower Established in 2000 to protect IP
  being developed at ASU and demonstrate technical
  feasibility
• 3 international patents already issued and 3 more
  pending as a result of gt 1.5M in federally
  funded research at ASU
• Since 2005 we have been awarded 5 SBIR/STTR
  contracts from DARPA, NASA, SFAz and NIH totaling
  705k- 1.5M of Phase II funding is pending
• Si FET technology demonstrated at three
  commercial foundries and two government labs

6
Summary Financials
Forecasted Revenue, Gross Margin Income
Product Revenue
7
Our Team

• Steven Wood CEOgt 20 years experience in the
  power components industry.Has successfully led
  several businesses in the power electronics
  industry which have been acquired at attractive
  valuations.
• Trevor Thornton, PhD Founder and President of
  SJT Micropower.Currently professor of Electrical
  Engineering at ASU with 24 years experience
  designing and testing novel semiconductor devices
• Seth Wilk, PhD Senior Engineer ASU PhD 2005
  RF/Low noise circuit design
• William Lepkowski Senior Engineer PhD
  Candidate in EE, ASU MESFET layout and
  characterization
• Asha Balijepalli Principal RF Engineer PhD
  Candidate in EE, ASU. She has held engineering
  internship positions at Freescale where she has
  worked on LD-MOS power amplifier design.

Retained Osborne-Maledon as legal counselSeeking
CFO candidates
8
Proposition
We are seeking 2.5M in funding over the next 18
months to develop prototypes in sufficient volume
to begin marketing in the US in Q3 2009.
Research
Development
Commercialization
Discovery
Technical
Integration
Prototype
Production
Feasibility
SJT Micropower SiFET technology
Full business plan and financials available on
request