RSIM: An ExecutionDriven Simulator for ILPBased SharedMemory Multiprocessors and Uniprocessors

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RSIM An Execution-Driven Simulator for
ILP-Based Shared-Memory Multiprocessors and
Uniprocessors

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Introduction

• RSIM - the Rice Simulator for ILP Multiprocessors
  RSIM is a discrete
  event-driven simulator based on YACSIM library
• Purpose Primarily
  designed to study shared-memory multiprocessor
  architectures built from state-of-the-art
  processors

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Architecture Features

• Processor Microarchitecture
• The Cache and Memory System
• The Multiprocessor System

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Processor features

• Multiple instruction issue
• Out-of-order (dynamic) scheduling
• Register renaming
• Static and dynamic branch prediction support
• Non-blocking loads and stores
• Speculative load execution before address
  disambiguation of previous stores
• Simple and optimized memory consistency
  implementations

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RSIM Processor Microarchitecture
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Memory hierarchy features

• Two-level cache hierarchy
• Multiported and pipelined L1 cache, pipelined L2
  cache
• Multiple outstanding cache requests
• Memory interleaving
• Software-controlled non-binding prefetching

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Multiprocessor system features

• CC-NUMA shared-memory system with directory-based
  cache-coherence protocol
• Support for MSI or MESI coherence protocols
• Support for sequential consistency, processor
  consistency, and release consistency
• Wormhole-routed mesh network

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The RSIM Memory System
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RSIM Implementation

• Event-driven simulation library
• Processor out-of-order execution engine
• Processor memory unit
• Cache hierarchy
• Directory and memory module
• Interconnection system

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The RSIM Memory and Network System

• Memory hierarchy and Interconnection system
• Cache hierarchy
• Directory and Memory Simulation
• System Interconnects

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Memory Hierarchy and Interconnection System
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Cache hierarchy

• First Level of Cache-L1
• Either write-through with no-write-allocate or
  write-back with write-allocate
• Second level of Cache
  
• Write-back with write-allocate
• Maintaining inclusion of L1

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Cache coherence Protocol

• MSI
• An explicit upgrade message is required
• MESI
• A message to be sent to the directory on
  elimination of an exclusive line from the L2
  cache is required.

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Supported Cache Coherence Protocols
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Directory and Memory Simulation

• The directory is responsible for maintaining the
  current state of a cache line, serializing
  accesses to each line, generating and collecting
  coherence messages, sending replies, and handling
  race conditions.
• The directory coherence protocol used in RSIM
  relies on cache-to-cache transfers and uses
  replacement messages

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System Interconnects

• Node bus
• Connects L2 cache, network interface,and the
  directory/memory modules within node
• Network Interface Modules
• modules that connect each nodes local bus to the
  interconnection network
• Multiprocessor Interconnection Network
• Separates request and reply networks for deadlock
  -avoidance

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Statistics in RSIM

• Overall performance statistics
• Other processor statistics
• Cache, memory, and network statistics