Why does dlx look this way

1
Why does dlx look this way?

• Why these forms of addressing
• Why this size of immediate value?

2
Addressing
mode
Example instruction
Meaning
When used
Register
Add R4,R3
RegsR4

RegsR4
When a value is in a register.
RegsR3
Immediate
Add R4,3
RegsR4

RegsR43
For constants.
Displacement
Add R4,100(R1)
RegsR4

RegsR4
Accessing local variables.
Mem100RegsR1
Register deferred
Add R4,(R1)
RegsR4

RegsR4
Accessing using a pointer or a
or
indirect
MemRegsR1
computed address.
Indexed
Add R3,(R1 R2)
RegsR3

RegsR3
Sometimes useful in array
MemRegsR1RegsR2
ad
dressing
R1
base of array
R2
index amount.
Direct or
Add R1,(1001)
RegsR1

RegsR1
Sometimes useful for accessing
absolute
Mem1001
static data address constant may
need to be large.
Memory indi
rect
Add R1,_at_(R3)
RegsR1

RegsR1
If
R3
is the address of a pointer
or
memory
MemMemRegsR3
p
, then mode yields
p
.

deferred
Autoincrement
Add R1,(R2)
RegsR1

RegsR1
Useful for stepping through ar-
MemRegsR2
rays within a loop.
R2
points to
RegsR2

RegsR2
d
start of array each reference in-
crements
R2
by size of an ele-
ment,
d
.
Auto-
Add R1,Ð(R2)
RegsR2

RegsR2Ð
d
Same use as autoincrement.
decrement
RegsR1

RegsR1
Autodecrement/increment can
MemRegsR2
also act as push/ pop to imple-
ment a stack.
Scaled
Add
RegsR1

RegsR1
Used to index arrays. May be
R1,100(R2)R3
Mem100RegsR2Regs
applied to any indexed address-
R3
d

ing mode in some machines.
FIGURE 2.5
Selection of addressing modes with examples,
meaning, and usage.
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(No Transcript)
4
Displacement bits
5
Alternative Architectures

• Design alternative
• provide more powerful operations
• goal is to reduce number of instructions executed
• danger is a slower cycle time and/or a higher CPI
• Sometimes referred to as RISC vs. CISC
• virtually all new instruction sets since 1982
  have been RISC
• VAX minimize code size, make assembly language
  easy instructions from 1 to 54 bytes long!

6
Evolution of Instruction Sets
Single Accumulator (EDSAC 1950)
Accumulator Index Registers
(Manchester Mark I, IBM 700 series 1953)
Separation of Programming Model from
Implementation
High-level Language Based
Concept of a Family
(B5000 1963)
(IBM 360 1964)
General Purpose Register Machines
Complex Instruction Sets
Load/Store Architecture
(CDC 6600, Cray 1 1963-76)
(Vax, Intel 432 1977-80)
RISC
(Mips,Sparc,HP-PA,IBM RS6000, . . .1987)
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A "Typical" RISC

• 32-bit fixed format instruction (3 formats)
• 32 32-bit GPR (R0 contains zero, DP take pair)
• 3-address, reg-reg arithmetic instruction
• Single address mode for load/store base
  displacement
• no indirection
• Simple branch conditions
• Delayed branch

see SPARC, MIPS, HP PA-Risc, DEC Alpha, IBM
PowerPC, CDC 6600, CDC 7600, Cray-1,
Cray-2, Cray-3
8
A dominant architecture 80x86

• See your textbook for a more detailed description
• Complexity
• Instructions from 1 to 17 bytes long
• one operand must act as both a source and
  destination
• one operand can come from memory
• complex addressing modes e.g., base or scaled
  index with 8 or 32 bit displacement
• Saving grace
• the most frequently used instructions are not too
  difficult to build
• compilers avoid the portions of the architecture
  that are slow
• what the 80x86 lacks in style is made up in
  quantity, making it beautiful from the right
  perspective

9
80x86

• 1978 The Intel 8086 is announced (16 bit
  architecture)
• 1980 The 8087 floating point coprocessor is
  added
• 1982 The 80286 increases address space to 24
  bits, instructions
• 1985 The 80386 extends to 32 bits, new
  addressing modes
• 1989-1995 The 80486, Pentium, Pentium Pro add a
  few instructions (mostly designed for higher
  performance)
• 1997 MMX is addedThis history illustrates
  the impact of the golden handcuffs of
  compatibility

10
Instruction Set Architecture

• Consider the RISC/CISC approaches
• DLX RISC example
• Intel x86 family as a CISC example
• What constitutes a good architecture?
• Consistency or doing similar things in a similar
  way
• Regularity or architectural features applied in a
  consistent fashion
• Completeness or having features that are
  necessary
• Parsimony or not having more than the necessary
  features
• Orthogonality or features sets are independent of
  one-another
• Transparency or low level functions do not affect
  higher-level ones
• Open-endedness or being expandable

11
Alternative Architectures
?1998 Morgan Kaufmann Publishers

• Design alternatives
• How to provide more powerful operations
• Improve performance by reducing number of
  instructions executed
• The danger is a slower cycle time and/or a higher
  CPI
• This alternatives become apparent when
  considering RISC vs. CISC architectures
• Virtually all new instruction sets since 1982
  have been RISC
• Counter example the VAX
• Minimized code size, make assembly language easy,
  complex instructions from 1 to 54 bytes long!
• We will consider several alternatives

12
Alternative Architectures
?1998 Morgan Kaufmann Publishers

• Design alternatives
• How to provide more powerful operations
• Improve performance by reducing number of
  instructions executed
• The danger is a slower cycle time and/or a higher
  CPI
• This alternatives become apparent when
  considering RISC vs. CISC architectures
• Virtually all new instruction sets since 1982
  have been RISC
• Counter example the VAX
• Minimized code size, make assembly language easy,
  complex instructions from 1 to 54 bytes long!
• We will consider several alternatives

13
(mem, operand) for alu

• (0,3) an alu operation has no memory ref, 3
  operands
• Dlx alpha, sparc (register-register) better clock
  cycles
• (1,2) x86
• Register mem
• (2,2) Vax
• (0,0) java jvm
• Stack compact

14
RISC - Reduced Instruction Set Computer

• Roots
• CDC 6600 (Seymour Cray)
• IBM 801 (John Cocke)
• U.C. Berkeley RISC (David Patterson)
• Stanford MIPS(John Hennessey)
• Commercial systems
• MIPS 2000
• HP Precision Architecture minicomputers (900
  series)
• IBM PC-RT and PowerPC
• Sun SPARC
• Alpha
• ______________________ Microprocessor without
  Interlocked Pipe Stages

15
RISC (Contd)

• Microprocessors
• AMD 29000 (1987)
• Motorola M88000 (1988)
• Intel i860 (1989)
• Now accepted by almost every manufacturereven
  ones who formerly embraced CISC

16
RISC Characteristics

• No universally accepted definition
• Most of the following
• Instructions are conceptually simple
• Instructions are of a uniform length
• Instructions use one (or very few) instruction
  formats
• Instruction set is orthogonal
• Little overlapping of instruction functionality
• Instructions use very few addressing modes
• Architecture is a load-and-store architecture
• Only LOAD and STORE instructions reference memory
• All operate instructions are register-to-register
• The ISA supports few data types

17
RISC Characteristics, (Cont'd).

• Other possible attributes
• Almost all instructions execute in one clock
  cycle
• Implementation detail
• Architecture takes advantage of strengths of
  software
• All reasonable architectures do
• Architecture should have many registers
• Not part of RISC
• Useful, however, for speeding up CPU

18
VAX 11/780 Characteristics

• Data point for comparison with RISC
• Over 400 instructions
• Varying length
• Up to 6 operand specifiers
• 16 addressing modes
• Many data types, including
• 6 types of integers
• 4 types of floating point
• Packed decimal strings
• Character strings
• Variable-length bit fields
• Numeric strings

19
CISC Advantages

• Arguments favoring CISC advanced by proponents
• Improved architectural merit, since operations
  implemented in hardware execute faster than those
  in software
• More complex instruction sets do not increase
  financial cost of implementation over simpler
  instruction sets
• Upward compatibility
• Richer instructions sets simplify compiler design
• Smaller, faster programs
• Complex instruction sets hinder cloning,
  protecting proprietary designs

20
CISC Advantages - Counter Arguments

• Some of the previous arguments are now outdated
• Main memory is now faster and cheaper
• Cache can take the place of microcode
• Think of cache as dynamic microcode
• Upward compatibility available through software
• Operating system rewriting
• Source code recompilation
• Simulation
• Complex instructions
• Dont necessarily match requirements of compilers
• Increased complexity of
• Control unit
• Pipelines
• Interrupt handling

21
CISC code size

• CISC programs not necessarily much smaller
• Results of three studies in early 80s(reported
  in William Stallings, Computer Organization and
  Architecture Principles of Structure and
  function, second edition, New York Macmillan
  Publishing Company, 1990, page 522)

22
RISC Advantages

• Arguments favoring RISC advanced by proponents
• Basic hardware is simpler, thus cheaper and
  faster
• Instruction caches compensate for larger number
  of bits in RISC instructions
• Easier target for compiler
• Design effort is less, thus development cost is
  less
• Easier to introduce parallelism into control unit