Analog Cable for D0 run 2B Silicon Tracker Layer 0

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Analog Cable for D0 run 2B Silicon Tracker Layer 0
Kazu Hanagaki Fermilab

• concept
• design issue (capacitance and space)
• prototype
• performance
• summary and prospect

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General concept

• SVX4 chip cannot sit on the sensors because of
  the cooling issues.
  ? Signal must be
  read out from the sensor to the chip. Also bias
  voltage and its return must be provided.

The longest 435mm
The shortest 243mm
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Cable design (noise due to capacitance load)
Total noise estimates VS total capacitance (Csi
Ccable)
S/N10
CSi
Ccable
S/N10 after 15fb-1 ? Ccable lt 23pF for 43.5cm
long cable
? Ccable lt 0.53pF/cm
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Cable design (capacitance calculations)
50 mm pitch
100 mm pitch
16 mm wide trace with 100 mm pitch satisfies the
requirement of lt0.53pF/cm

• 50 mm thick Kapton substrate (er 3.5).
• Copper trace with 8 mm height.
  ? Calculation agrees with
  measurement with 10 for the 1st prototype.

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Capacitance calculations
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Prototype design

• 91mm trace pitch
• 16mm trace width
• Two cables work as a pair for one sensor.

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Other issues

• Spacer between the cables.
  ? polypropylene mesh spacer. (er 1.5)
• Need a shield for pick-up noise protection.
  Aluminum foil? Copper? Thickness? Mesh? ? Note
  yet decided. More study needed.
• HV and its return traces will be solder masked.

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Radiation length

• (a) 16 of area occupancy is taken account.
• (b) 50 of volume occupancy assumed. May be
  possible to reduce.
• (c) heavy duty aluminum foil was measured to 20mm
  thick.

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Dyconex cables
By Frank Lehner

• performed a visual inspection on cables
• look for not gold-plated (copper) pads as
  evidence for an open trace
• results on 12 cables
• 6 cables w/ zero open
• 4 cables w/ 1 open trace
• 2 cables w/ 2 open traces
• check trace width on cables
• 9-14 mm depending on cable

Capacitance (one to neighbors) is measured to be
0.35pF/cm.
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Layer 0 prototype using the analog cable
3 chip HDI (run2A) with SVX2
ELMA L0 prototype
Purple is wire bonding.
Aluminum foil to the back plane
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Noise performance
Noise increase peak(1)peak(2)/2 - peak(3)
0.79
Chip 1
Chip 2
Chip 3
SVXII noise expectatoin 490e 50e C(pF)
Chip 1
Chip 2
Chip 3
Csi 10pF Ccable 15pF
1.2 ADC counts??
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Summary and Plan

• The cable design is settled. This works
  mechanically and with reasonable noise
  performance.
• Capacitance or noise measurement with stacking of
  cables.
• Dyconex prototype is not so bad.
• However, it has not yet cleared the
  specification (opens). Besides my little worry
  is the higher capacitance of 2nd prototype than
  expectation.
• We will have 10 more prototype cables soon.
• Look for the backup vendor such as Compunetics.