Timothy A' Osmulski, John K' Antonio, Jason Bivins, Nikhil D' Gupta, Jack M' West, and William M' Ma

1
Timothy A. Osmulski, John K. Antonio, Jason
Bivins, Nikhil D. Gupta, Jack M. West, and
William M. MarcyTexas Tech UniversitySupported
by DARPA Contract No. F30602-97-2-0297Optimal
Configuration of Combined GPP/DSP/FPGA Systems
for Minimal Size, Weight, and Power
A Power Prediction Simulator for FPGAs

• Feedback Circuits Require Symbolic Iteration of
  Probability Expressions
• Assume pa , pb , pe are known then pd and pc
  are determined using iteration

• Power Consumption Model for a Transistor Gate
  Pavg 1/2 CV 2 f A

pclock 0.50 Aclock 1.0
p123 0.10 A123 0.13

p12 0.83 A12 0.17

x1x2 x3
x1x2
Iteration 1 pd pa pc pa pe Iteration 2 pd
pa pa pb pe pc (pa pe pa pb pe) pe pa pe
Iteration 3 pd pa pa pb pe pc pa pe
pd
pa
d
a
d
p1 0.88 A1 0.10
x1
c
x1
pb
b
e
pe
c
x2
p2 0.29 A2 0.17
x2
d a bc
c d e
pc
x3
p3 0.69 A3 0.27
x3

• Surface Temperature versus Frequency

• Physical Connections between CLBs in an FPGA
  Implementation

• Convergence Achieved for all Circuits Tested

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Simulator Transforms Physical Connections to
Logical Connections among Local and Remote Signals
180
165
LUT
150
Temperature (F)
4
LUT
135
120
LUT
0
10
20
30
40
50
Interconnection Fabric
LUT
Frequency (MHz)
LUT

• The simulator estimated 125mW 43.6mW/MHz

LUT

• Instrumentation for Surface Temperature
  Measurements