LVDS - PowerPoint PPT Presentation
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Title:
LVDS
Description:
out 0.5ns to 3.0ns. Data setup to clock 2.5nS. Data hold time 0.5nS. Information from National DS90C385. DOTCLK# DCLK/2. DCLK/2# DRGB. 10nS. Assume. 100MHz ... – PowerPoint PPT presentation
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Title: LVDS
1
Assume 100MHz Dotclk
LVDS Transmitter
LX
DRGB(240)
HSYNC
VSYNC
DISPLAY ENABLE
LVDS Transmitter
DRGB(240)
Hook up all 24 bits
D-type FF
Data setup to clock 2.5nS Data hold time
0.5nS Information from National DS90C385
Clock to out 0.5ns to 3.0ns
Clock to DRGB out 0.5ns to 3.0ns
This is not the absolute requirement. However the
FF Timing must be close to this.
10nS
DOTCLK
DCLK/2
DCLK/2
DRGB
Odd Data
Odd Data
Odd Data
Even Data
Even Data
