Lessons Learned The Hard Way: FPGA ? PCB Integration Challenges

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Lessons Learned The Hard Way FPGA ? PCB
Integration Challenges

• Dave Brady Bruce Riggins

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Agenda

• Design Overview
• Design Challenge Summary
• Lessons Learned
• Suggested Strategies

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System Design Challenges

• Complex system implemented using multiple
  high-pin count FPGAs
• PCB bus speeds gt 150 Mhz
• PCB physical size restricted
• Implementation team (s)
• System design, 2 engineers
• System architecture, Embedded CPU h/w design
• PCB design, 1 engineer
• Functional design, PCB timing, PCB signal
  integrity
• PCB physical design, 1 engineer
• PCB place and route, design for manufacturing
• FPGA design, 5 engineers
• RTL HDL development
• DSP design, 1 engineer
• C algorithm development
• Embedded software development, 2 engineers

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Conceptual Design Overview
PCB
DRAMMemoryModules
FPGA Boot Module
FPGA 1
CPU Embedded Platform
Glue Logic
Custom (ASIC) Logic
Voltage Regulators/Generators
FPGA 2
Clock Generators
Custom (ASIC) Logic
DSP
Glue Logic
Communication Module
Communication Module
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Design Challenge Summary

1. Overdriven signals
2. Cross talk
3. Simultaneous switching outputs
4. Meeting system performance specifications
5. Minimizing PCB manufacturing costs
6. Learning the FPGA device-specific I/O design
   rules
7. Maintaining (updating) FPGA symbols for the PCB
   schematic
8. Leveraging the complete design team

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Lessons Learned Increasing PCB CostsStarted
with FPGA Timing

• FPGA 1 pin-to-pin timing exceeded spec by 100 ps
• FPGA designer increased drive strength
• Pin-to-pin timing meets spec

PCB
FPGA 1
FPGA 2
Tp gt Spec by 100 ps
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Increasing PCB CostsInduced Signal Ringing on
PCB (contd.)

• Increasing drive strength on FPGA 1 output pin
  induced PCB signal ringing
• PCB engineer identified

PCB
FPGA 1
FPGA 2
Tp lt Spec
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Increasing PCB CostsInduced Signal Ringing on
PCB (contd.)

• PCB engineer began inserting termination networks
• Results
• ? PCB component count
• ? PCB via count
• ? PCB trace count
• ? PCB routability
• ? PCB costs

PCB
R
FPGA 1
FPGA 2
Tp lt Spec
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Lessons Learned Increasing PCB Costs --Scoping
the Problem

• Not an issue for a single trace
• Design contained four 64-bit high-speed data
  busses
• All 256 signals were impacted!

PCB
B1data(063)
FPGA 1
FPGA 2
B2data(063)
B3data(063)
Tp lt Spec
B4data(063)
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Lessons Learned Big Busses ? Cross Talk

• Busses laid out on PCB with matching trace (tp)
  lengths
• Identified by the PCB engineer
• Traditional solutions
• Increase trace-to-trace separation
• Leverage lower-dielectric PCB laminates

PCB
B1data(0)
FPGA 1
FPGA 2
B1data(1)
B1data(2)
Tp lt Spec
B1data(63)
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Lessons Learned Big Busses ? Simultaneous
Switching Outputs

• Grouping busses into the same pin bank improves
  PCB routability
• FPGA pin banks are limited in the current they
  may source
• Leads to SSO issues

PCB
B1data(063)
FPGA 1
FPGA 2
B2data(063)
B3data(063)
Tp lt Spec
B4data(063)
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Balance is the Key
FPGA I/O Drive Strength Setting
Signal Too Slow
Signal Ringing
FPGA I/O Rail Voltage Setting
Simultaneous Switching Output Issues
Signal Cross Talk
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Lessons Learned Leveraging I/O Flexibility

• Both FPGA devices designed to specs
• Unable to meet system timing specs

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Leveraging I/O Flexibility (contd.)

• Changed the physical location of signals on the
  FPGA
• Unable to meet timing in one FPGA

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Leveraging I/O Flexibility (contd.)

• Changed the physical location of signals (again)
• Finally met system timing specs
• Simple for a single signal ? Complex for wide
  busses

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Lessons Learned The Domino Effect of Pin Swapping
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1
2
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All Pins Are Not The Same
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Virtex II Pro Input AC Characteristics
Source Xilinx website
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Virtex II Pro Input AC Characteristics
Source Xilinx website
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Virtex II Pro Input AC Characteristics
Source Xilinx website
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Resolving Symbol Size
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Synchronizing the FPGA PCB Flows
Physical Placement Connectivity
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Multiple Perspectives That Dont Match

• FPGA and PCB design teams typically do not
  communicate

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Suggested Strategies Eliminate Team
Communication Barriers
We do the FPGA I/O Design
System Designer
PCB (Schematic) Designer
We do the FPGA I/O Design
We do the FPGA I/O Design
FPGA Designer
Embedded System (CPU) Designer
PCB Layout
We do the FPGA I/O Design
We do the FPGA I/O Design
We do the FPGA I/O Design
PCB Timing Analysis
DSP Designer
We do the FPGA I/O Design
PCB Signal Integrity
We do the FPGA I/O Design
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General Tips Tricks

• Leverage Signal Integrity What if Analysis
  Early
• Anticipate signal ringing, cross talk, ground
  bounce, etc.
• Develop system constraints to minimize PCB
  components
• Make trade-offs at the system level
• Run Signal Integrity Analysis on the PCB Design
• Interactive part of the normal design process
• NOT a design verification check box
• Leverage Embedded Resistors
• Some signal termination is un-avoidable
• Minimize PCB size
• Reduced PCB costs
• Leveraging Gigabit Transceivers Reduces PCB
  Traces BUT
• GHz signals ? High-Speed ( cost) PCB laminates
• Introduces additional PCB components (clock
  generators, voltage regulators, etc)
• Introduces additional termination topology
  requirements
• Re-partition the FPGA Design to Optimize PCB
  Performance
• Alternative to leveraging Gigabit transceivers
• Will not work for every design
• Worked for this design

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Routing Comparison
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PCB Layer Reduction
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Reduce Overall System Design Time

• Concurrent design of FPGA and PCB
• Optimize system performance reduce
  manufacturing costs
• Solution Bi-directional FPGA I/O design

FPGA design

• I/O Designer
• Reduced Design Time
• Enhanced System Integration
• Optimized Performance
• Lowered Manufacturing Costs

PCB design
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Provide PCB Designers an Intelligent FPGA I/O
Design Tool
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Show FPGA Designers the PCB Design
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Provide Everyone Detailed Control
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Automate Pin Planning
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I/O Design Planning Benefits
Output to Setup Pass
Clock to Output Pass

• Meet performance constraints
• Overall timing constraints
• FPGA in-chip
• On board
• PCB signal integrity constraints
• Comply with FPGA technology I/O rules
• Eliminate PCB signal layers

Board Interconnect Budget FAIL
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The Complete Flow Including PCB Physical Design

• Flow Integration
• Schematic to layout
• Layout to I/O pin planning
• FPGA Designer has visibility into the PCB design
• PCB designer has access to I/O design rules
• Fast pin swaps
• Automatic bus untangling