ARINC 429 with a Host Processor on an FPGA

1
ARINC 429 with a Host Processor on an FPGA

• 2005 MAPLD International Conference
• September 2005
• Paper 236
• Ian Land
• Ryan Mohan

2
Introduction

• Trends
• Technological advances in semiconductor size and
  speed, coupled with the demand for custom logic,
  has led to the use of FPGAs to implement several
  systems on one chip.
• Electronic Bus Systems
• ARINC 429, MIL-STD-1553 and Ethernet-MAC are used
  in systems with data link layer controller and
  host processor (uP)
• ARINC 429, a low-speed standard, requires no more
  than an 8-bit host processor
• An FPGA with integrated Data Link Controller and
  Host
• There are many considerations to be made when
  interfacing an ARINC 429 bus Interface to a host
  processor, including
• Glue logic
• Application code

3
ARINC 429 Overview

• ARINC 429 Standard
• ARINC 429 is a two-wire, point-to-point data bus
  that is application-specific for commercial and
  transport aircraft.
• Words are 32 bits in length and are transmitted
  at either 12.5 or 100 kbps to other system
  elements monitoring the 429 bus.
• ARINC 429 uses a unidirectional data bus standard
  - the Mark33 Digital Information Transfer System
  with Tx Rx on separate ports
• Actel ARINC 429
• Provides a complete Transmitter (TX) and Receiver
  (RX) solution for up to 16 Tx and 16 Rx channels
  per the ARINC 429-16 specification
• Each channel has selectable data rate and label
  memory size
• Selectable system clock
• Programmable interrupt and FIFO generation
• Internal wrap-around testing
• Requires external (standard) ARINC 429 line
  drivers and line receivers to interface to the
  ARINC 429 bus.
• An external host CPU is necessary to set up the
  cores control registers and initialize the label
  memory.
• Consists of three main blocks Transmit, Receive,
  and CPU Interface.

4
ARINC 429 IP Core

• Bus Interface a 32-Bit Data Word
• 32nd Bit is the parity bit
• SSM is the Sign/Status Matrix
• ARINC Data formats are commonly encoded as Binary
  Data (BNR) and Binary Coded Decimal (BCD)
• SDI, the Source Destination Identifier,
  specifies the intended receiver
• The lower 8 Bits specify label word
• Varies depending on the particular equipment and
  systems that require interconnection

5
ARINC 429 IP Core

• CPU Interface - direct CPU access to memory
• The Internal Registers can be read/written via a
  9-Bit CPU address
• Channel Number can range from 0 to 15
• Tx/Rx Bit specifies whether a Tx or Rx register
  is being addressed
• Register Index specifies which Core429 internal
  register is being addressed
• RX Registers 0 Data Register TX
  Registers 0 Data Register
• 1 Control Register 1 Control Register
• 2 Status Register 2 Status Register
• 3 Label Memory 3 Unused
• Byte Index is used to control CPU read/writes
  depending on the CPU datapath width (4 operations
  for 8-bit CPU, 2 for a 16-bit CPU, 1 for a 32-Bit
  CPU)
• Easily interfaced to the Actel 8-bit 8051 uP

6
8051 8-Bit Processor IP Core

• Overview
• High performance, single-chip, 8-bit
  microcontroller.
• Features
• Some of the key features are
• 32-Bit I/O Ports
• Serial Port
• Two 16-Bit Timer/Counters
• Interrupt Controller Four Priority Levels with
  13 Interrupt Sources
• Internal Data Memory Interface
• External Memory Interface
• Optional On-Chip Instrumentation Debug Logic
• Optional Power-Saving Modes

7
8051 Processor IP Core

• Internal Special Function Registers (SFRs) hold
  data and control the timer, interrupts and serial
  ports
• Four separate memory regions accessible to the
  CPU
• DATA
• 256 bytes of memory used for dynamic storage of
  program data such as register, stack, and
  variable data. Typically, only the lower 128
  bytes are directly addressable for program data.
  Addressing the upper 128 bytes points to the SFR
  memory region.
• CODE
• 64 KB of memory used for program storage and
  interrupt vectors.
• XDATA
• 64 KB of memory used for storage of large data
  sets, custom-designed peripherals, and extended
  stack space if necessary.
• SFR
• Upper 128 bytes of DATA space is a combination of
  internal core memory and external memory used for
  internal and external SFRs.

8
ARINC 429 IP Interfaced to 8051 uP

• System overview
• 8051 IP is host CPU for ARINC 429 Bus Interface
  IP
• Implemented on one FPGA and integrated alongside
  other Intellectual Property to create a single
  chip solution.
• Depends on the existence of easy to use interface
  logic
• The 8051 SFR Interface
• The 429 CPU Interface

9
429 Interfaced to a 8051 uP

• Interface Logic 8051 SFR Interface
• Can service up to 101 External SFRs
• External SFRs can be used to interface with an
  off-core peripheral, such as an ARINC 429 Bus
  Interface Core.
• Such a peripheral can use all addresses from the
  SFR address space range 0x80 to 0xFF except those
  already implemented within Core8051 as Internal
  SFRs.
• Although the SFR address space contains 8-bit
  addresses, the external SFRs are addressed by a
  7-bit address which corresponds to the 8-bit
  internal address with the MSB removed.

External Special Function Register Interface
10
429 Interfaced to a 8051 uP

• Interface Logic 8051 SFR Interface
• Due to the restricted memory map, an indirect
  addressing capability was created
• Use memory-mapped registers (external SFRs) to
  hold the Core429 9-Bit CPU address and the
  corresponding data.
• This 429-to-8051 system implements 4 external
  SFRs
• The 9-Bit CPU address requires two of the 8-Bit
  SFRs
• Leaves one SFR with 7 unused bits, providing a
  convenient means for control/handshaking
  functions.
• One SFR is used for data written to the 429 Bus
  Interface IP from the 8051 Host and one SFR for
  data read by the Host 8051

11
429 Interfaced to a 8051 uP

• Interface Logic - ARINC 429 IP CPU Interface
• Allows the system CPU (8051 IP) to
• Read/Write ARINC data to the ARINC 429 IP
  internal FIFO
• Access the 429 control and status registers
• Write to the 429 internal label memory
• This system requires that the 429 IP be
  configured with a CPU_DATA_WIDTH of 8 Bits to
  interface to the 8-Bit 8051 CPU

12
429 Interfaced to a 8051 uP

• Interface Logic Glue Logic
• Advantage Only a small amount of glue logic is
  needed to integrate the IP Cores if the 8051 and
  the ARINC 429 cores are in the same clock domain
• This system (with 4 TX and 4 RX channels) is
  physically implemented on an Actel Development
  Board where both cores operate off a common 16
  MHz clock.

13
429 Interfaced to a 8051 uP

• Interface Logic Glue Logic
• Physically connects 429 IP to 8051 IP Host
• Enforces a communication protocol between the two
  cores
• In this Core429-Core8051 System, the 4 SFRs used
  (0x40, 0x41, 0x42, 0x43) are mapped to
  WRITE_ADDRESS0, WRITE_ADDRESS1, WRITE_DATA,
  READ_DATA respectively

14
429 Interfaced to a 8051 uP

• Interface Logic Glue Logic
• Implementation
• Decodes the sfraddr input from the 8051 Host by
  comparing against the predefined memory-map
• Controls the handshaking between the 8051 Host
  and 429 IP
• Accumulates the 9-Bit CPU address from the 2
  address SFRs and sends it to Core429
• Passes data between Core8051 and Core429
  according to the protocol discussed
• The verilog implementation of this logic is
  available for viewing
• 8051 Application Code
• The system is able to execute user programs
  written in C and cross-compiled into 8051
  assembly code
• Application code that uses ARINC 429 functions
  must follow the communication protocol discussed
• Sample application code is available for viewing

15
Verification

• Verified cores individually
• Against datasheet and ARINC standard
• 100 Code Coverage target
• Simulated the system
• Verify the interface between the cores
• HW/SW co-verification could help verification of
  ARINC data transfers
• Takes a substantial effort and long simulation
  run times
• Tested the hardware
• Efficient method was to program the FPGA and run
  the software
• Found no handshake between 8051 and ARINC 429 bus
  interface
• Reviewed the design after unsuccessful handshake
• Reviewed logic analyzer data, focused on 8051 SFR
  interface
• Changed communication protocol, re-designed
  glue-logic and changed application code
• Handshake occurred

16
Verification (p2)

• Application software tests Core429 to host CPU
• Early SW write read ARINC 429 data to
  individual registers
• Interface through RS-232 and hyper terminal on a
  PC
• More sophisticated software after handshake
• Loopback test and communication with 4 TX / 4 RX
  channels
• Once the handshake worked
• Internal FPGA loop back test
• Verify off-chip, but within the development
  platform
• Send signal from daughter cards transmit to
  receive connections
• Connect to ARINC 429 tester to debug, verify and
  validate
• With FPGA, we checked different ARINC 429
  configurations (loopback, etc.)

17
Verification (p3)

• Test against standard
• System vs. ARINC 429 data monitor
• TX- SW terminal interface via RS-232 to host CPU,
  which instructed Core429 to send data to the
  tester via transmit channels
• RX Tester sent ARINC data word to the bus which
  was received by FPGA where we monitored RX FIFO
  with terminal

18
429 IP Core Interfaced to a M68K

• System Overview
• A small amount of glue logic is needed to connect
  the 429 CPU Interface to the M68K address and
  data buses

19
429 IP Core Interfaced to a M68K

• Several considerations for interfacing
• Match Clocks - ie. 20 MHz
• Match CPU_DATA_WIDTH on Core429 to 16-bit M68K
  data bus width
• Consider how the 429 Internal Registers and
  Memory are addressed and accessed
• Directly mapping the 429 9-bit address to the
  relatively large M68K address bus is an effective
  solution
• Requires that a 9-Bit address space in the M68K
  memory map be reserved for communication with the
  429 Bus Interface IP
• For example, 0x00000000-0x000001FF, could be
  reserved unless this address space is
  pre-reserved by the M68K or another device
• Note that there can be up to 8 TX and 8 RX ARINC
  429 channels implemented while the MSB of the
  9-Bit 429 CPU address will remain zero
• CPU Interface
• The 429 CPU Interface would perform the same
  function as in the 429-8051 system
• Based on the variation of M68K used, the width of
  the cpu_dout and cpu_din signals will be have to
  be adjusted accordingly

20
429 IP Core Interfaced to a M68K

• Interface Logic Glue Logic Block Diagram
• The glue logic block interfaces the 429 CPU
  Interface to the M68K address and data bus.
• This block is required to follow a communication
  protocol that adheres to the M68K bus
  communication protocol

21
429 IP Core Interfaced to a M68K

• Interface Logic Glue Logic
• One possible communication protocol is shown
  below
• Note The above description is for a 16-Bit
  read/write. 32-Bit ARINC 429 data operations
  require two read/write operations with the
  appropriate CPU address and data.
• During 8-Bit operations (on the 429
  control/status registers, and label memory) only
  one of either UDS or LDS will be asserted at a
  time.

22
429 IP Core Interfaced to a M68K

• Interface Logic Glue Logic/Application Code
• Another important consideration for an ARINC
  429-to-Host CPU system is its application
• Many applications are better implemented by using
  interrupts to indicate to the CPU that an ARINC
  429 event has occurred
• The 429-8051 system is part of a terminal
  interface that continually waits for user
  commands, via a keyboard
• Thus the register polling approach is acceptable
• Most applications favor the use of interrupts
  over the register polling approach used in the
  429-8051 system
• Interrupts will free up the host CPU to perform
  other operations and functions
• To completely specify the glue logic between the
  429-to-M68K system, the interrupt lines IPL0,
  IPL1, and IPL2 need to be interfaced with the 429
  Bus Interface IP Core
• If interrupts are used, the M68K assembly code
  used for 429 operations would reside in an
  Interrupt Subroutine (ISR)

23
Lessons Learned

• Integrating cores is not a simple connect
• Multiple Clock Domains
• Single clock domain is the simplest, fastest and
  safest
• Address and Data Bus Widths
• How much address space does the core require
  relative to that available ?
• Does the core have the same data bus width as the
  processor ?
• What about performance
• At what rate does the processor need to access
  the core
• Does it require direct access
• Is slow polled access possible
• Application code must match the system and
  protocol
• System simulation is required
• You should always run system-based simulations
• It is quicker and better than trying to debug the
  FPGA in hardware
• Can try more configurations than on board
  (loopback, 4/4, 16/16)
• Customers and local FAEs also verified 4/5, 4/8
  and many other variations
• A design is not integrated until it is hardware
  tested
• Core429/Core8051 would not communicate in HW
• Additional debugging of IP and application SW
  code for handshake