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Device Modeling for RFIC Design/Simulation

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Device Modeling for RFIC Design/Simulation Chapter 14 Behavior Model for RF/MS Simulation & VerilogA Language T.H.Huang A Switched Inductor VCO s Behavior: * Need a ... – PowerPoint PPT presentation

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Title: Device Modeling for RFIC Design/Simulation


1
Device Modeling for RFIC Design/Simulation
Chapter 14 Behavior Model for RF/MS
Simulation VerilogA Language
T.H.Huang
2
References
1 ???, Mixed-Signal IC Design Kit Training
Manual, CIC ?? ??. 2 Affirma Verilog-A
Language Reference, by Cadence, July 2001. 3 A
Lecture Verilog-A Language, by William Vides.
3
  • General
  • A system usually contains both digital and
    analog parts
  • Gate counts ? Digital gtgt Analog (gtgtRF)
  • Co-Simulation trade-off between
  • time efficiency and
    performance accuracy.

4
  • Conventional Design Flow
  • Three Design Domain in Gajskis Y-Chart

Algorithm System Design
Structural Logic Design
Transistor-Level Design
Layout Design
5
  • Conventional Design Flow (cont.)
  • Digital (VLSI) System Design Top ? Down

System Level Design/Simulation
Behavioral Level Design / Simulation
Register Transfer Level (RTL) Design/Simulation
Logic Synthesis
Gate Level
Logic Level Design/Simulation

Switch Level
Layout Design
Post-Layout Verification
6
  • Conventional Design Flow (cont.)
  • Analog/RF System Design Bottom ? UP

System Integration Simulation
Architecture Decision
Function Block Design
Circuit Structure Design/ Simulation
Transistor/Component Selection
Layout Design
Post-Layout Verification
7
  • Mixed-Signal Top-Down Design Flow
  • Not really for performance prediction but for
    function prediction!

System Design/Simulation
Architecture Decision
Function Block Design/Simulation
Circuit Structure Design/Simulation
Transistor/Component Selection
Layout Design
Post-Layout Verification
8
  • A Complete Top-Down Design Methodology
  • Using a Mixed-Signal Simulator

9
  • The Goals of Mixed-Signal Simulation
  • The system behavior verification
  • The system requirement check
  • The system performance evaluation
  • Evaluate if a certain architecture is better than
    others for the system
  • -- Easier to implementation
  • -- Better performance ( power / speed / noise /
    etc.)
  • -- Lower cost ( area / less BOM)
  • Simulation time efficiency (since digital
    simulation only in time domain)
  • -- Fourier transform for frequency domain.

10
  • Analog Systems
  • Nodes
  • Conservative Systems whose each node has two
    values

  • associated with it the potential of
  • the node
    and the flow out of the node.
  • Obey
    both KVL and KCL.
  • Reference Nodes GND
  • Reference Direction
  • Signal-Flow System associated only a single
    value with each node.
  • Ex. like a
    logic state machine.
  • Mixed Conservative and Signal-Flow Systems

11
  • What is Required for Mixed-Signal Simulator?
  • Is the simulation result reliable? ? algorithm,
    methodology
  • Is the algorithm stable? ? easy to converge
  • Is the model appropriated? ? device model
    supporting, A/D interface
  • the simulators completeness? ? design format,
    supported languages
  • The simulators efficiency? ? time and accuracy

12
  • Analog Modeling Issues
  • The model can predict the circuit function in
    both time and frequency
  • domains
  • Less parameters to support a simple model for
    providing enough
  • information
  • The complete model for a block in the system may
    be difficult. However,
  • it is possible to join some blocks as a new
    block with a simple model
  • for simulation

13
  • Commercial Tools Available
  • Cadence
  • -- Affirma VHDL/Verilog, Verilog-A, Spectre
  • -- AMS VHDL/Verilog, Verilog-A,
    VHDL/Verilog-AMS, Spice/Spectre
  • Mentor
  • -- ADVance MS (ModelSimEldo) C,
    VHDL/Verilog, Verilog-A,

  • VHDL/Verilog-AMS, Spice
  • Synopsys
  • -- VCSNanoSim C, VHDL/Verilog, Verilog-A,
    Spice

14
  • Verilog-A an Analog Hardware Description
    Language
  • Compatible with Verilog Language
  • An extension version to describe the behavior
    models for analog blocks
  • An OVI (Open Verilog International) Standard
  • An multidiscipline language that models
    electrical, mechanical,
  • fluid dynamics, and thermodynamic system (with
    feedback function)
  • Supporting the Top-Down Design concept.

15
  • Verilog-A Modeling Approaches

1. Structure Model
  • a Module concept

Module cap(p,n) Capacitor (.c(c_value)) Cmin
(p,n) endmodule
2. Behavior Model
Module cap(p,n) Analog begin I(p,n) lt
ddt(c_valuev(p,n)) end endmodule
Structure Model
(Netlist-like type)
3. Mixed Structure Behavior Model
16
  • Basic Programming

(interface declarations)
(Main Description Body)
17
  • Built-in Mathematical Functions
  • Standard Mathematical Functions ln(), log(),
    exp(), sqrt()

  • min(), max(), abs(), pow(x,y)xy

  • floor(), ceil()
  • Trigonometric and Hyperbolic Functions sin(),
    asin(), sinh(),

  • hypot(x,y)sqrt(x2y2)

18
  • Some useful statements

(1) Procedural Assignment Statement l_expr
expression Ex. V_out Va Vb (2)
Branch Contribution Statement b_value lt
expression Ex. V(n1,n2) lt expr1 expr2
(3) Indirect Branch Assignment
Statement target equations Ex. V(out)
V(n1, n2) 0
that means find V(out) such that V(n1,n2) is
zero
19
  • Some useful statements (cont.)

(4) Conditional Statement if (conditions) else
(5) Case Statement case (expression)
default endcase (6) Repeat Statement repeat
(repeat_num) (7) While Statement while
(expression) (8) For Statement for
(initial expression step)
20
  • Detecting and Using Analog Events
  • Four Analog Events initial_step, final_step,
    cross(), timer()
  • Using _at_(analog_event) statement
  • only when analog_event occurs, the simulator
    runs statement
  • Otherwise, statement is skipped.

21
  • Some analog operators
  • The time derivative operator ddt(expr, abstol
    nature)
  • The time integral operator idt(expr, assert,
    abstol nature)
  • The circular integrator operator
  • idtmod(expr, ic, nodulus, offset,
    abstolnature)
  • Delay operator absdelay(expr, time_delay,
    max_delay)
  • Transition Filter
  • transition(expr, delay, rise_time,
    fall_time, timetol)

22
  • A Verilog-A File Example for digital VCO

23
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24
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25
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26
Detect only zero Crossings where the Value is
increasing!
27
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28
  • A Demo for a PLLs Locking Time investigation
  • PLL analog ? LPF, VCO digital ? prescaler,
    PFD, CP
  • A good example who contains both digital and
    analog
  • But VCO prescaler, the associated output is
    digital-like,
  • thus we generate a square wave VCO, as a
    behavioral
  • oscillator. ? Behavior model concept.
  • Question In a MB-OFDM UWB system, the sub-band
    carriers
  • are in a hopping operation, where the time slot
    for hopping is
  • only 9.5ns. You want to know if you can use a
    phase-lock architecture
  • to provide the hopping carriers?

29
  • In general, the locking time of a traditional PLL
    is about
  • in the order of micro-seconds
  • In this demo example, we just find a VCOs
    locking time needed
  • from 1.2GHz to 1.3GHz. It is not for the UWB
    application.

VCOs spec center_freq 1.2 GHz
vco_gain 100 MHz
vlogic_high 2 V
vlogic_low 0 V Divider /12 or /13 LPF
R1 11 K, C1 94 pF, and C2 9.1 pF. CP
iamp_inc 0.1 mA iamp_dec 0.2 mA
30
  • Schematic of a PLL

31
  • Loop Locked

fosc fref x 13 100MHz x 13 1.3
GHz
32
  • Locking Time Required for Up-Jump (1.2GHz ?
    1.3GHz)

Lock Time 6 us, simulated
33
  • Locking Time Required for Down-Jump (1.3GHz ?
    1.2GHz)

Note ?V 1.05 V
Lock Time 5.5 us, simulated
34
  • A Switched Inductor VCOs Behavior

Need a modified Verilog-A file for SW_VCO.
(1.45V)
(0.4V)
35
  • Locking Time Required for Up-Jump (1.2GHz ?
    1.3GHz)

Lock Time 3.5 us, simulated
36
  • Locking Time Required for Down-Jump (1.3GHz ?
    1.2GHz)

Lock Time 9.0 us, simulated
Note ?V 55 mV
37
  • Conclusions
  • The decrease of lock time is due to the different
  • operation of VCOs
  • Proper design can speed up both up- and down-jump
  • lock time, if using dynamic tuning of LPF.
  • In general, the carrier generation for MB-OFDM
    UWB
  • application, the PLL architecture may not
    satisfy the
  • hopping speed requirement.
  • This demo just shows the potential of
    investigating
  • the system requirement using behavior model.

the end
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