Low Power Design of CMOS Circuits

1
Low Power Design of CMOS Circuits

• Vishwani D. Agrawal
• James J. Danaher Professor
• ECE Dept., Auburn University, Auburn, AL 36849

2
CMOS Logic (Inverter)
No static leakage path exists for either 1 or 0
input.
F. M. Wanlass and C. T. Sah, Nanowatt Logic
using Field-Effect Metal-Oxide-Semiconductor
Triodes, IEEE International Solid-State Circuits
Conference Digest, vol. IV, February 1963, pp.
32-33.
3
Power of a CMOS Gate Transition
VDD
Dynamic Power CLVDD2/2 Psc Static power
VDD Ileakage
R
Vo
Vi
CL
R
isc
Ground
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Power Consumption of VLSI Chips
Why is it a concern?
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ISSCC, Feb. 2001, Keynote
Ten years from now, microprocessors will run at
10GHz to 30GHz and be capable of processing 1
trillion operations per second about the same
number of calculations that the world's fastest
supercomputer can perform now. Unfortunately,
if nothing changes these chips will produce as
much heat, for their proportional size, as a
nuclear reactor. . . .
Patrick P. Gelsinger Senior Vice
PresidentGeneral Manager Digital Enterprise
Group INTEL CORP.
6
VLSI Chip Power Density
Suns
Surface
Hot Plate
Source Intel?
7
Low-Power Design

• Design practices that reduce power consumption by
  at least one order of magnitude in practice 50
  reduction is often acceptable.
• Low-power design methods
• Algorithms and architectures
• High-level and software techniques
• Gate and circuit-level methods
• Test power

8
Components of Power

• Dynamic
• Signal transitions
• Logic activity
• Glitches
• Short-circuit
• Static
• Leakage

Ptotal Pdyn Pstat Ptran Psc Pstat
Then Ptran Psc Pstat Now
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Dynamic Power

• Each transition of a gate consumes CV 2/2.
• Methods of power saving
• Minimize load capacitances
• Transistor sizing
• Reduce transitions
• Logic design
• Glitch reduction

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Glitch Power Reduction

• Design a digital circuit for minimum transient
  energy consumption by eliminating hazards

Total transitions 6 Essential transitions
2 Glitch transitions 4
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Multi-Input Gate
Delay D lt DPD
A B
DPD Differential path delay
C
A B C
DPD
D D
Hazard or glitch
time
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Balanced Path Delays
Delay D lt DPD
A B
DPD
C
Delay buffer
A B C
D
No glitch
time
13
Glitch Filtering by Inertia
Delay D gt DPD
A B
C
A B C
DPD
D gt DPD
Filtered glitch
time
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Designing a Glitch-Free Circuit

• Maintain specified critical path delay.
• Glitch suppressed at all gates by
• Path delay balancing
• Glitch filtering by increasing inertial delay of
  gates or by inserting delay buffers when
  necessary.
• A linear program optimally combines all
  objectives.

Path delay d1
Delay D
Path delay d2
Minimum transient energy condition d1 d2 lt D
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Linear Program (LP)

• Variables gate and buffer delays, arrival time
  variables.
• Objective minimize number of delay buffers.
• Subject to overall circuit delay constraint for
  all input-output paths.
• Subject to minimum transient energy condition
  for all multi-input gates.

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An Example Full Adder
1
1
1
1
1
1
1
1
1
Critical path delay 6
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LP Step 1 Define Varaibles

• Gate delay variables d4 . . . d12
• Buffer delay variables d15 . . . d29
• Arrival time variables (earliest) t4 . . . T29
• (longest) T4 . . . . T29

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LP Step 2 Specify Constraints

• For Gate 7
• T7 T5 d7 t7 t5 d7 d7 gt T7 - t7
• T7 T6 d7 t7 t6 d7

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LP Step 2 (Cont.)
Buffer 19

• T16 d19 T19
• t16 d19 t19

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LP Step 2 Critical Path Constraints

• T11 maxdelay
• T12 maxdelay
• maxdelay is specified

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LP Step 3 Define Objective Function

• Need to minimize the number of buffers.
• Because that leads to a nonlinear objective
  function, we use an approximate criterion
• minimize ? (all buffer delays)
• i.e., minimize d15 d16 d29
• This gives near optimum results.

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LP Solution maxdelay 6
1
2
1
1
1
1
1
2
1
2
2
Critical path delay 6
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LP Solution maxdelay 7
3
1
1
1
1
1
2
2
1
2
Critical path delay 7
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LP Solution maxdelay 11
5
1
1
1
1
3
2
3
4
Critical path delay 11
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ALU4 Original and Glitch-Free
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C7552 Circuit Spice Simulation

• Power Saving Average 58, Peak 68

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Components of Power

• Dynamic
• Signal transitions
• Logic activity
• Glitches
• Short-circuit
• Static
• Leakage

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Leakage Reduction Problem
65nm CMOS technology Low threshold transistors,
gate delay 5ps, leakage current 10nA. High
threshold transistors, gate delay 12ps, leakage
1nA. Minimize leakage current without increasing
critical path delay. What is the percentage
reduction in leakage power? What will be leakage
power reduction if 30 critical path delay
increase is allowed?
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Solution 1 No Delay Increase
Reduction in leakage power 1
(41710)/(1110) 32.73 Critical path delay
25ps
12ps
5ps
12ps
5ps
5ps
5ps
5ps
5ps
12ps
5ps
12ps
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Solution 2 30 Delay Increase
Several solutions are possible. Notice that any
3-gate path can have 2 high threshold gates. Four
and five gate paths can have only one high
threshold gate. One solution is shown in the
figure below where six high threshold gates are
shown with shading and the critical path is shown
by a dashed red line arrow. Reduction in leakage
power 1 (61510)/(1110) 49.09 Critical
path delay 29ps
12ps
5ps
5ps
12ps
12ps
5ps
12ps
5ps
12ps
5ps
12ps
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Integer Linear Programming (ILP) to Minimize
Leakage Power

• Assign every gate i an integer 0,1 variable Xi.
• Define ILP constraints and objective function
• On critical path delay
• Minimize total leakage
• Let ILP find values of Xis
• If Xi 1, assign low threshold to gate i
• If Xi 0, assign high threshold to gate i

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Power-Delay Tradeoff
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Leakage Dynamic Power Optimization 70nm CMOS
c7552 Benchmark Circuit _at_ 90oC
Leakage exceeds dynamic power
Y. Lu and V. D. Agrawal, CMOS Leakage and Glitch
Minimization for Power-Performance Tradeoff,
Journal of Low Power Electronics (JOLPE), vol. 2,
no. 3, pp. 378-387, December 2006.
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Power Constrained Test Scheduling
R1
R2
M2
M1
R3
R4
A datapath
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Minimum Test Time
LFSR1
LFSR2
T2 test for M2
M2
M1
Test power
T1 test for M1
MISR1
MISR2
Test time
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Minimum Test Power
R1
LFSR2
M2
M1
Test power
T1 test for M1
T2 test for M2
MISR1
MISR2
Test time
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Testing of MCM and SOC

• Test resources Typically registers and
  multiplexers that can be reconfigured as test
  pattern generators (e.g., LFSR) or as output
  response analyzers (e.g., MISR).
• Test resources (R1, . . .) and tests (T1, . . .)
  are identified for the system to be tested.
• Each test is characterized for test time, power
  dissipation and resources it requires.

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Resource Allocation Graph(A Bipartite Graph)
T1
T2
T3
T4
T5
T6
R2
R1
R3
R4
R5
R6
R7
R8
R9
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Test Compatibility Graph (TCG)
T1 (2, 100)
T2 (1,10)
T6 (1, 100)
T3 (1, 10)
T5 (2, 10)
T4 (1, 5)
Power
Test time
Tests that form a clique can be performed
concurrently.
Pmax 4
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Find All Cliques in TCG
CLIQUE NO. i TEST NODES TEST LENGTH, Li POWER, Pi
1 T1, T3, T5 100 5
2 T1, T3, T4 100 4
3 T1, T6 100 3
4 T1, T5 100 4
5 T1, T4 100 3
6 T1. T3 100 3
7 T2, T6 100 2
8 T2, T5 10 3
9 T3, T5 10 3
10 T3, T4 10 2
11 T1 100 2
12 T2 10 1
13 T3 10 1
14 T4 5 1
15 T5 10 2
16 T6 100 1
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Integer Linear Program (ILP)

• For each clique (test session) i, define
• Integer variable, xi 1, test session selected,
  or xi 0, test session not selected.
• Constants, Li test length, Pi power.
• Constraints to cover all tests
• T1 is covered if x1x2x3x4x5x6x11 1
• Similar constraint for each test, Tk
• Constraints for power Pi xi Pmax

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ILP Objective and Solution

• Objective function
• Minimize S Li xi
• all cliques
• Solution
• x3 x8 x10 1, all other xis are 0
• Test session 3 includes T1 and T6
• Test session 8 includes T2 and T5
• Test session 10 includes T3 and T4
• Test length L3 L8 L10 120
• Peak power max P3, P8, P10 3 (Pmax 4)

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Summary

• Underlying theme in our research use of
  mathematical optimization methods for power
  reduction at gate level
• Dynamic power
• Leakage power
• Power minimization under process variation
• Test power
• Other research
• Min-max power estimation
• Architecture level power management

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Our Research Students

• T. Raja, MS 2002, PhD 2004 (NVIDIA)
• S. Uppalapati, MS 2004 (Intel)
• F. Hu, PhD 2006 (Intel)
• Y. Lu, PhD 2007 (Intel)
• J. D. Alexander, MS 2008
• K. Sheth, MS 2008
• M. Allani, PhD
• J. Yao, PhD
• K. Kim, PhD
• M. Kulkarni, MS

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Dissertations and Papers

• Dissertations
• http//www.eng.auburn.edu/vagrawal/THESIS/thesi
  s.html
• Papers
• http//www.eng.auburn.edu/vagrawal/TALKS/talks.
  html