Wiring Layer Assignments with Consistent Stage Delays

1
Wiring Layer Assignments with Consistent Stage
Delays

• Andrew B. Kahng (UCLA)
• Dirk Stroobandt (Ghent University)
• Supported by Cadence Design Systems, Inc. and
• the MARCO Gigascale Silicon Research Center

2
Outline

• Introduction wiring layer assignment
• Problem and models
• Optimization objective function
• Our layer assignment method
• Discussion and results
• Conclusion

3
Introduction

• DSM design routing tools have to account for
• delay constraints
• yield
• power
• Conventional technique
• router assigns wires to layers
• wire sizing, repeater insertion/sizing applied
• More interesting approach
• wire sizing etc. used by router to assign wires

4
Our Layer Assignment Concept

• Search for optimal layer for a wire with
• optimal wire size, number and size of repeaters
  for each wire
• meeting consistent stage delay constraints
• taking total repeater area constraint into
  account
• accounting for impact of vias
• A priori estimation techniques make it useful for
  application both before / after placement
• Potential applications
• improving CAD layout tools
• studying effects of technological parameters
• optimizing fabrication process

5
Problem and Models
Find the optimal assignment of wires to
wiring layers subject to delay constraints and
total repeater area constraints

• Optimization objective of layers needed
• Degrees of freedom (for each wire)
• choice of layer parameters
• wire width
• number of repeaters
• size of the repeaters

6
Layer Assignment Assumptions

• layer pairs form tiers (H and V)
• tiers grouped in tier types
• (equal parameters)
• (even) number of layers/type to be determined
• wires are routed on 1 tier
• inputs to the method
• number of tier types and their layer parameters
• order (bottom-to-top) user-defined
• output
• optimal number of layers / tier type
• layer to which wires are assigned

7
Delay Constraint Model

• Sakurais IEEE TED, 1993 delay equation
• depends on wire length/width through wire R, C
• Delay can be reduced by
• increasing wire width (for fixed length and
  layer)
• consider uniform wire sizing (no tapering)
• continuous wire sizing (no discrete set of
  widths)
• optimal gate sizing
• repeater insertion and sizing
• repeaters at equal distances
• number of repeaters even
• Trade-off between delay and area

8
Via Impact Model

• Sai-Halasz 1995 every layer blocks 15
• Newer models
• Chong 1999, Chen 1999
• terminal vias and turn vias
• each wire uses 2 via stacks
• number of terminal vias defined by layer
  assignment model
• Via impact factor
• Chong Chen

9
Wire Length Distribution

• All wires classified according to their length
• Wire length distribution needed
• measuring distances between placed gates
• applying a priori wirelength estimation

10
Cost Function Number of Layers

• Non-integer by considering area needed/tier
• A available area/layer
• Area parts wiring area area lost to vias

Tier type i
11
Cost Function (cont.)

• Via area assumptions
• square area with side minimal wire width/layer
• line of vias for wider wires
• via sizes scale with minimal wire widths for
  lower layers

Tier type 2
Tier type 1
Tier type 0
12
Cost Function (cont.)

• Number of vias
• each repeater adds 2 vias on layer of tier below
• each repeater adds 1 via on layer of own tier
• no repeaters as if 1 repeater

Gate
Repeater
Wire on type 2
Tier type 1
Tier type 2
13
Via Impact Limits Number of Layers

• Via impact factor must be lt 1
• For maximum number of layers (e.g., 10)
• 8 layers for wires flt0.2
• number of wires lt 300,000
• (250nm, 10M trans., logic area 54mm , 4mm wire
  pitch on tier, all wires minimum width, no
  repeaters)

2
14
Layer Assignment method

• 2 phases optimize, then round to integers
• Phase 1

Calculate minimal delay Tmin.
15
A Typical Example
Tier type 2
Tier type 1
Tier type 0
Wire width (mm)
Delay (ps)
0
2
4
0
0
2
2
4
Number of repeaters
Wirelength (mm)
16
Target Delay Influence
Tier type 2
Tier type 1
Tier type 0
Delay (ps)
Wire width (mm)
Wirelength (mm)
Wirelength (mm)
17
Uniform Versus Non-uniform Stacks

• Uniform still 3 numbers via impact Li fi

18
Optimal Layer Stack Monotonic?

• Results depend on delay constraint

19
Conclusions

• Layer assignment is becoming more critical
• Our proposal use stage delay constraints
• Current work 2-D length-delay distribution
• Wire/repeater sizing via impact area limit
• Via impact severely limits number of wires
• Interesting conclusions
• maximum wire width on tier type not dependent on
  delay constraint
• monotonic non-uniform layer stack
  (fat-wires-on-top) better than uniform
• non-monotonic worse for tight delay constraints
  but non-fat tier on top can be beneficial
• Useful to search for optimal layer stack
  parameters
• Find threshold values to ensure optimality of
  layer stack and make layer assignment more
  trivial