VSV: L2MissDriven Variable SupplyVoltage Scaling for Low Power

1
VSV L2-Miss-Driven Variable Supply-Voltage
Scaling for Low Power

• Hai Li, Chen-Yong Cher, T. N. Vijaykumar, and
  Kaushik Roy
• ECE Department, Purdue University
• International Symposium on Microarchitecture 2003

2
Outline

• Introduction
• Contributions
• Circuit-level issues
• Microarchitectural issues
• Simulations and results
• Conclusions

3
Introduction

• Supply-voltage scaling is an effective dynamic
  power reduction technique
• Dynamic power can be reduced by VDD2
• Microarchitectural observations
• Upon a cache miss, processor executes only the
  few instructions that are independent of the miss
  and often ends up stalling, despite out-of-order
  issues, etc.
• VDD transition times are of the same order ad
  L2-hit latencies(e.g. 12cycles for Alpha 21264)
• L2 miss penalties are long enough(e.g. 100
  cycles)

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Introduction(contd.)

• VSV(Variable Supply-Voltage scaling)
• Lowering the VDD on L2 cache misses
• Depending upon programs degree of ILP
• Targeting high-performance processors ( gt 1Ghz)
• Overview of VSV
• L2 cache miss triggers VSV
• Upon a miss, instruction issue rate is checked
• If issue rate meets the given threshold, scaled
  voltage and frequency are applied till the miss
  returns
• Few instructions,independent of the cache miss,
  are executed slower at the lower VDD

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Contributions

• Circuit level
• VSV considers two level of VDD , VDD transition
  time overhead, and the energy overhead of scaling
  RAM structures supply voltages
• Architectural level
• VSV uses L2 misses and an instruction-issue-rate
  monitoring mechanism as triggers for VDD
  transitions

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Circuit-level issues

• Choice of supply voltages
• Set VDDH to 1.8V
• Set VDDL to 1.2V through HSPICE simulation in
  TSMC 0.18um technology
• Rate of change of supply voltages
• Through transistor-level conditions, switching
  between VDDH and VDDL costs 12 cycles (TSMC 0.18
  um and 1GHhz clock)

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Circuit-level issues(contd.)

• Power-supply network
• Used a dual-power-supply network to achieve fast
  VDD switching
• Varying the clock speed
• Clock distribution
• The whole die is reachable within 2ns(2cycles)
• ? Transmit control signal to the root of clock
  
• tree clock propagation 4ns
• Keep the PLL operating at VDDH
• PLLs settling time is on the order of 10100us
• To change clock speed, a counter as a frequency
  divider is used

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Circuit-level issues(contd.)

• Varying the VDD of RAM structures
• Voltage scaling is not applied to large RAM
  structures(register file, I-cache, D-cache)
• During an access, only a small fraction of the
  cells are accessed. But, in scaling all the cells
  either charges or discharges
• ? Amortization is not possible by scaling
• Combinational logic achieves power saving by
  scaling
• Level conversion on the path from VDDH to VDDL
• Level-converting latches are needed between the
  RAM structures and the pipeline
• To mitigate the delay, multiplexing the regular
  and level-converting latch

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Microarchitectural issues

• Sections of processor
• RAM structures(gray) do not apply VSV
• All the other sections(white) apply VSV
• Structure diagram of VSV

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Microarchitectural issues(contd.)

• High-power mode
• Processor operates at VDDH and full clock-speed
• High-to-low power mode transition
• Down-FSM
• When an L2 miss signal reaches the processor, FSM
  starts
• FSM records the instruction-issue rate for small
  period
• If the no. of consecutive cycles in which no
  instruction is issued is above a threshold(e.g.
  15 cycles),that is in low ILP state, transition
  to low-power mode starts

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Microarchitectural issues(contd.)

• Low-power mode
• Pipeline operates at VDDL and half clock-speed
• Register file and L1 cache operate at the half
  clock-speed and VDDH
• Low-to-high power mode transition
• Up-FSM
• When an L2 miss data returns to the processor,
  FSM starts
• FSM records the instruction-issue rate for small
  period
• If the no. of cycles in which at least one
  instruction is issued is above a threshold(e.g.
  15 half-clock-speed cycles),that is in high ILP
  state, transition to high-power mode starts

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Microarchitectural issues(contd.)

• Time line High-to-low power mode transition
• Time line Low-to-high power mode transition

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Simulations

• Used Wattch to simulate an 8-issue, out-of-order
  processor for evaluating VSV
• Estimated processor power for 0.18um technology
• Baseline processor configuration
• Used Alpha-SPEC2K benchmark programs

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Results

• On average, VSV achieves 7 power saving with 1
  performance degradation

SPEC2K benchmark statics
VSV results w/wo FSM
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Results(contd)
Effects of thresholds on high-to-low transition
Impacts of Time-Keeping Prefetching on VSV
Effects of thresholds on low-to-high transition
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Conclusions

• Proposed a novel variable supply-voltage
  scaling(VSV) technique to reduce processor power
  without undue impact on performance
• VSV scales down the supply voltage of certain
  sections of the processor during an L2 miss while
  being able to carry on the independent
  computations at a lower speed
• VSV saves 7 in total processor power for all
  SPEC2K benchmarks with 0.9 performance
  degradation