Electronics for PS and LHC transformers

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Electronics for PS and LHC transformers

• Grzegorz Kasprowicz
• Supervisor David Belohrad
• AB-BDI-PI
• Technical student report

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Why new PS transformers electronics is needed?

• Current calibration procedure doesn't allow full
  scale calibration on the low sensitivity range -gt
  source of error
• It does not support remote adjustments (required
  by LHC)
• Calibrators work only in manual mode require
  operator in place they are installed during
  calibration procedure

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PS integrators following conceptions were built
and tested

• Analogue integrator solution based on diode
  switches and high speed OPAMPs
• Analogue integrator solution based on IVC102U
  integrated chip
• Digital solution based on High Speed ADCs

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Analogue integrators prototype board
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Analogue integrator 1

• This version was implemented using diode switches
  driven by current switches.
• The linearization block that compensates diode
  switches nonlinearities was used
• High speed voltage feedback opamps were used
• Linearity results meet PS needs

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Integrator 1 linearity results
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Analogue integrator 2

• Based on IVC102U chip, which integrates
  operational amplifier, switches and capacitors.
• Too slow for PS application minimum integration
  time is 30us while 5us is needed it saturates
  output when clocked too fast.

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Digital integrator

• Existing project PCBs (CCD camera) were used. It
  consists of FPGA, 8051 microcontroller with USB
  2.0 interface, SDRAM memory, power supply, 2x
  12bit 210MS/s ADC, configuration and program
  EEPROM, input amplifiers.
• The input signal is sampled and integral over
  specified period is calculated digitally in FPGA.
  Then the result is stored in RAM and transferred
  to PC via USB

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Digital integrator prototype board- existing
project was used
USB 8051
Program EEPROM
2x ADC 12bits 210MHz
USB Connector
FPGA
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Digital integrator linearity results
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Digital Integrator

• Linearity measured meets PS requirements, but
  there is expected further improvement caused by
  proper clocking and noise.
• This version was chosen to realization as final
  prototype due to its simplicity, reliability and
  measurement parameters.

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Digital integrator - advantages

• No precision analog components required, only
  input amplifier, Low Pass Filter and ADC driver
• Linearity guaranteed by ADC
• Good thermal stability
• Simplicity fewer component count that improves
  reliability
• Thanks to FPGA, function of device can be changed
  remotely

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Linearity measurement test bench

• Integrators 1 and 2 were connected to digital
  integrator board to simplify measurements
• Simple control application working under Windows
  was written to allow easy control of integrators
  parameters and results acquisition

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Testbench
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Control application
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PS Calibrators following conceptions were
built and tested

• Charge calibrator with 200V DC/DC converter
• Current calibrator switched current source
  4A/200V

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PS charge calibrator

• How does it work?
• Disadvantages
• Newer version of existing calibrator instead of
  mechanical switch, MOSFET was used. This allows
  remote operation
• Integrated 12V/300V DC/DC converter that
  simplifies supply

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Charge calibrator prototype
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PS current calibrator

• How does it work?
• Disadvantages
• There was built adjustable pulse current source
  0..4A / 50 Ohm
• Switch on/off time lt100ns
• Problems with thermal stability, linearity and
  transients occurred improved solution with
  compensation was developed
• Prototype was built using discrete components
  (transistors only), improved version uses CFA and
  MOS drivers

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PS current calibrator
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VME Intensity measurement system for PS

• Compact single board solution based on VME bus
• Integrated current/charge calibrator
• Integrated HV DC/DC converter
• Based on FPGA technology ensures high flexibility
• Two high speed ADCs working in parallel
• System can be used for another data acquisition
  applications
• All functions and adjustments controlled
  remotely
• - Integration delay, gate time
• - calibration delay, pulse width, gate time
  delay
• - offset compensation gate delay, analogue
  compensation
• - calibrators voltage and current
• - .

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VME board block schematic
Input Filter And Attenuator
FPGA
BUFFERS
ADC 12bit 210Ms/s
IN
VME
ADC 12bit 210Ms/s
Power Supply 1.5V 2.5V 3.3V 5V -5V
programmable DC/DC 12V/200V converter
Current calibrator Programmable pulse current
Source 0..4A,max 200V
OUT I
Charge calibrator Switched capacitor
OUT Q
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VME integrator parameters

• VME 32bit interface
• FPGA 6k Logic Elements
• 2xADC 12 bit,210Ms/s with LVDS
• All VME signals are buffered
• HV DC/DC converter 0..200V programmable range
  with output voltage monitor
• Pulse current source 0..4A programmable range
• 10.5 ENOB with 50 Ohm input short
• Linearity better than 0.2
• Offset compensation (analog and digital)

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VME integrator - prototype
2x ADC 12bit,210MS
DC/DC converter
LPF
Calibrators
FPGA
Supply regulators
Bus buffers
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VME board final version
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VME measurement system status

• The new board is assembled and soon will be ready
  for tests
• The single test software running on VME
  controller is written
• The software group (M.Ludwig, J.J.Gras) is
  working on drivers

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VME board final version

• Ready-made PCB shielding used
• Compensated current calibrator
• Current feedback controller in DC/DC converter
• Test outputs on the front panel
• Status LEDs on the front panel
• Polymer fuses added
• Board address selection switch
• Fixed minor bugs

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Fast integrator for LHC

• Existing integrated (LHC-2002) requires using 2
  or more channels to achieve 30dB of dynamic
  range. The improvement of dynamic range gives
  the possibility to use one measurement range only
• Low input voltage range
• Too high input voltage causes chip damage
• There is under development discrete solution

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Fast integrator for LHC version 1

• Based on diode switches driven by transformers
• 2 versions of diode drivers built and tested
  (integrated and discrete one)
• High speed VFA and CFA tested problems with
  stability occurred
• Discrete version of CFA developed problem with
  output range and power dissipation of used
  transistors
• Problem with too high reset time

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Fast integrator for LHC version 1
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Fast integrator for LHC version 2

• Solved problem with power limitation of
  transistors and output voltage range
• Still too high reset time (ECL logic used)
• Diodes replaced by MOSFET
• SRD solves problems with reset time still under
  development

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Fast integrator for LHC version 2 - block
schematic
Current follower
OUT
IN
ECL timing
CLK
Pulse trafo
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Fast integrator for LHC version 2
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Fast integrator for LHC version 3
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LHC integrator testbench

• Based on Cyclone FPGA Development KIT
• Small mezzanine module was developed
• 14bit, 60MS ADC drivers
• It was used to measure integrators linearity

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LHC integrator testbench
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LHC integrator linerity
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The following projects are currently under
development

• VME Intensity measurement system for PS
• Fast integrator for LHC (alternative for existing
  integrated solution)