TX79: A MIPSCompatible Synthesizable Core with Multimedia Vector Extensions

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TX79 A MIPS-Compatible Synthesizable Core
withMultimedia Vector Extensions

• Peter Hsu
• Toshiba America Electronic Components, Inc.

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System-On-a-Chip Challenges

• Technical
• High Performance Processor Core
• Large System Complexity
• Management
• Intricate Back-End Process
• Lingering Bug Fix Schedule
• Business
• Development Cost Containment

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Toshibas SOC Solution

• TX79 Processor Core
• Dual Issue, 128-Bit SIMD Datapaths
• Fully Synthesized, Standard Cells
• System Architecture
• Memory, Basic I/O Components
• Physical Design Methodology
• Absorb Last-Minute RTL Changes
• Preserve Physical Timing Optimizations

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TX79 Block Diagram
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TX79 Attributes

• MIPS Architecture
• 32 Bit Address
• 64 Bit Data
• 128 Bit Vector (ISA Extension)
• Streaming Data
• Nonblocking Prefetch
• Efficient
• 24mm2 (0.18um), 200MHz (w.c.)

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System Architecture
SDRAM Controller
CPU Bus
Processor Core
Customer Logic
Bridge
Peripheral Bus (64 bits)
SPI
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Physical Design Challenges

• Processor Core
• Speed Physically Based Optimizations
• Flexibility Shape, Routing Porosity
• Migration Standard Cells
• Complex Integrated System
• Manage Convergence
• Lingering Bug Fixes

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Tiles Scalable Methodology

• Necessity
• Chip 10M Gate
• Tools 1M Gate?
• Multifaceted
• Reusable Unit
• Independent Construction
• Fast Turnaround

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CAD Flow

• Master Plan
• Logical-Physical Gate Mapping
• Tile Dimensions
• Hard Macro Placement
• Pin Locations
• Parallel Flow

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Tiles Malleable, Reusable Unit

• Can Be Hard Macro
• Fixed, Dependable Timing
• Quantifiably Finished
• Can Be Reshaped
• Preserves Physically-Based Speed Tuning Effort
  (Relatively)
• Can Be Moved Around
• CPU Core Shape Flexibility

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Examples
U Shaped TX79
L Shaped TX79
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SOC Challenges Addressed

• High Performance Processor Core
• In Between Soft and Hard Macro
• Physical Speed Tuning
• Flexible Shape, Standard Cells
• Complex System
• Partitioned Construction Flow
• Rapid RTL to GDSII for Bug Fixes
• Manageable Process

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Complete SOC Solution

• Silicon Issues
• Building Blocks
• System Architecture
• Construction Methodology
• Other Issues
• Chip Packaging
• System Verification
• Manufacturing Test

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Chip Packaging

• Integrated CAD
• Artwork
• I/O Cell Placement
• Wire Bonding Coordinates
• Global Design
• PC Board, Package, Chip

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Summary

• TX79 Processor Core
• Powerful Dual-Issue Pipeline
• 128 Bit Multimedia Vector Operations
• 200MHz, 24mm2
• Complete SOC Solution
• Basic Building Blocks
• System Architecture
• Mature Methodology