Evaluating the Raw microprocessor

1
Evaluating the Raw microprocessor

• Michael Bedford Taylor
• Raw Architecture Group

Computer Science and AI Laboratory Massachusetts
Institute of Technology
2
Evaluating the Raw microprocessor

• Brief Overview of Raw Architecture
• Avenues of Evaluation
• Empirical - Comparison with P3
• Analytical - Modeling Large scale ILP
  Experiential - Experimental Systems

3
The Raw Architecture
Divide the silicon into an array of identical,
programmable tiles.
(A signal can get through a small amount of logic
and to the next tile in one cycle.)
4
Raw Architecture
Compute Processor
Routers
On-chip networks
5
Raw Architecture
Compute Processor
Routers
On-chip networks
6

Inside the compute processor networks are
integrated directly into the bypass paths
r24
r24
r25
r25
r26
r26
r27
r27
Output FIFOs to Static Router
Input FIFOs from Static Router
E
M1
M2
A
TL
TV
IF
RF
D
F
P
U
F4
WB
7
Raws bypass-integrated on-chip networks serve as
a Scalar Operand Network, or SON.
Multiple Raw tiles
Program graph
seed.0seed
seed.0seed
pval5seed.06.0
pval1seed.03.0
v1.2v1
pval1seed.03.0
v2.4v2
pval4pval52.0
pval5seed.06.0
pval2seed.0v1.2
pval0pval12.0
pval0pval12.0
tmp3.6pval4/3.0
pval3seed.ov2.4
pval4pval52.0
tmp3tmp3.6
tmp1.3pval22.0
tmp0.1pval0/2.0
tmp0.1pval0/2.0
tmp2.5pval32.0
v3.10tmp3.6-v2.7
tmp3.6pval4/3.0
tmp1tmp1.3
tmp0tmp0.1
tmp0tmp0.1
tmp2tmp2.5
v3v3.10
pval7tmp1.3tmp2.5
tmp3tmp3.6
pval6tmp1.3-tmp2.5
v1.8pval73.0
v2.4v2
v1.2v1
v2.7pval65.0
pval3seed.ov2.4
pval2seed.0v1.2
v0.9tmp0.1-v1.8
v1v1.8
v3.10tmp3.6-v2.7
tmp2.5pval32.0
tmp1.3pval22.0
v2v2.7
v0v0.9
tmp2tmp2.5
tmp1tmp1.3
v3v3.10
pval6tmp1.3-tmp2.5
pval7tmp1.3tmp2.5
v2.7pval65.0
v1.8pval73.0
v2v2.7
v0.9tmp0.1-v1.8
v1v1.8
v0v0.9
8
Empirical Evaluation Comparison to P3
Parameter Raw (IBM ASIC) P3 (Intel)
Litho 180 nm 180 nm
Process CMOS 7SF P858
Metal Layers Cu 6 Al 6
FO1 Delay 23 ps 11 ps
Dielectric k 4.1 3.55
Design Style Standard Cell Full custom
Initial Freq 425 MHz 500-733 MHz
Die Area 331 mm2 106 mm2
9
(No Transcript)
10
(No Transcript)
11
Analytical Evaluation Scalar Operand Network
Research (SONs). (See HPCA 2003 and future.)
12
Scalar Operand Network The network and the
associated algorithms that are responsible for
matching operands and operations In space.
13
SON Performance Metric 5-tuple
conventional lt3, 15, 2, 1,
12gt distributed multiprocessor
Superscalar lt 0, 0, 0, 0,
0gt (not scalable)
14
Raw a new point in the region.
conventional lt3, 15, 2, 1,
12gt distributed multiprocessor Raw SON
lt 0, 1, 1, 1, 0gt Superscalar SON lt
0, 0, 0, 0, 0gt (not scalable)
15
Impact of Receive Occupancy, 64 tiles,i.e.,
lt0,1,1,1,ngt
16
Experiential Evaluation (i.e., Real Hardware,
Real Systems)
Systems Online or in Pipeline Workstation Microp
hone Array Fabric System (Software Radio on
Raw) (IP Routing on Raw)
17
Raw Chip Specifications

• IBM SA27E Process
• 180 nm, 6-metal copper ASIC process
• 16 Tile RAW Processor
• 18.23mm x 18.23mm
• 1657 pin CCGA package
• 1152 HSTL signal pins
• Clock and Power
• 420MHz (actual)
• 10 watts (power save mode)
• 18 watts typical
• 35 watts max

18
Raw Motherboard
.. twenty-eight 32-bit buses connecting Raw Chip
to I/O and Memory System
19
2 Microphone Board
2 Microphones 1 A-to-D 1 CPLD 2 Connectors
20
1020 Element Microphone Array
21
Fabric System Architecture

• Design two distinct board types
• Board 1 Quad Raw Board
• Board 2 I/O Memory Board
• Replicate and connect

22
Summary