Verification Environment of Highspeed Serial Bus System

1
Verification Environment of High-speed Serial Bus
System

• Advisor
• Sy-Yen Kuo
• Speaker
• Kuan-Lin Chen

2
PCI Express Topology

• Root Complex (RC)
• Provides system BIOS enumeration and discovery of
  complete PCI system
• Provides realistic memory map of all devices in
  the system
• Variable number of root ports
• Switch
• Variable number of downstream ports
• Variable port width
• Endpoint (EP)
• Back-door API allows tests to be initiated by
  the endpoint
• Model actual endpoint device with memory, IO
  space, configuration space

3
PCI Express 2.0 Enhancement

• Gen2 speed negoitation
• Support 2.5 and 5.0 Gigabits / second / Lane /
  direction (both Gen. 1 and Gen. 2) serial data
  transmission rate.
• Trusted Configuration Space
• Access control services

4
Verification environment

• Complete system topologies
• Substitute DUT for one of our BFMs
• Verification environment supports adding new
  tests easily
• Powerful bug finders and debug features

5
Functional Coverage

• There are totally 1122 checklist items.
• Functional coverage is 84.95