Performance Debugging of Esterel Specifications

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Performance Debugging of Esterel Specifications

• Lei Ju
• Bach Khoa Huynh
• Abhik Roychoudhury
• Samarjit Chakraborty

School of Computing National University of
Singapore
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Synchronous languages

• Formalism for specifying reactive systems
• Predictable execution/response times
• Modeling highly concurrent systems
• e.g. Esterel, Lustre, Signal,
• Industrial usage SCADE suite

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Synchrony hypothesis

• Discrete view of time ticks
• Processing of all events occurring in a tick
• in zero time!
• Abstraction used by the programmer
• Need to be supported at the implementation level
• Hardware Synthesis
• Special-purpose processors
• What about general-purpose processors?

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Validating Synchrony Hypothesis

• Responses to events take non-zero time!
• Need to estimate execution time of the
  computation occurring in a tick
• Worst-case Execution Time Analysis
• Validate Synchrony Hypothesis, if
• WCET Inter-arrival separation time
• SW exec. of synch. spec. on GPP.
• Performance debugging via WCET results
• In todays talk
• Not a routine application of WCET analysis!

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Related Work

• Hardware Synthesis, e.g.
• G. Berry. Mechanized reasoning and hardware
  design, chapter Esterel on hardware.
  Prentice-Hall, 1992
• Special-purpose Processors, e.g. KEP
• X. Li and M. Boldt and R. von Hanxleden. Mapping
  Esterel onto a Multi-Threaded Embedded Processor.
  In Proceedings of the 12th International
  Conference on Architectural Support for
  Programming Languages and Operating Systems
  (ASPLOS06), San Jose, CA, October 2125 2006.
• Very recently (2008), moves towards GPP
• AbsInt and Esterel Technology tie-up.
• Our work on Esterel is the same space, with
  emphasis on
• Characterization of path patterns in
  automatically generated code
• Performance Debugging Support from binary code
  to Esterel

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Esterel

• Imperative style concurrent language
• Deterministic execution
• Usage/collaboration in/with
• Dassault Aviation, Cadence Design Systems, Texas
  Instruments, ..
• Lego Mindstorms Robots

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Compiling Esterel

• Control-flow graph based approach
• Esterel is imperative-like
• Schedule concurrency ? sequential code
• Scales well, fast code
• Generated C code
• Tick function loop-free ? 0-1 basic block count
• Common infeasible path patterns
• Characterize, detect and exploit them in WCET
  analysis of generated code

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Worst Case Execution Time

• Maximum execution time of a program on a
  micro-architecture for all possible inputs

Mature tools exist for WCET analysis of C
programs. Past Experience developed Chronos WCET
analysis tool (2001-06) http//www.comp.nus.edu.sg
/rpembed/chronos
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WCET State-of-the-art
Processor Configuration
C Binary
Control-flow Graph
Processor Configuration
Disassembly
Inter-procedural Control Flow Analysis
Infeasible Program Path Detection, Loop Bounds
Time Estimation of Basic Blocks
WCET Calculation (ILP)
WCET
ILP formulation of WCET problem
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Technical Problems Addressed

• How to automate WCET estimation of C code
  generated from Esterel?
• WCET of not the whole Esterel program
• Computation performed in a single tick!
• How to feedback WCET results for performance
  debugging at Esterel level?

Software execution of synchronous languages on
general purpose processors
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Methodology
Esterel spec.
WCET Critical path
Esterel compiler
C code (tick function)
C Binary
C compiler
WCET analyzer
Infeasible path detection

• 1. Automated infeasible path detection
• Generate constraints to eliminate them ? tighter
  WCET
• No need for loop bounds acyclic code!

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Methodology
Esterel spec.
WCET Critical path
Performance debugging
WCET refinement
Esterel compiler
C code (tick function)
C Binary
C compiler
WCET analyzer
Infeasible path detection

• 2. Performance Debugging
• Backwards traceability is a must !
• 3. WCET Refinement
• Provide additional environment constraints for
  tighter WCET

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Automated Inf. Path Detection
b0
x0 if (y)
(assignment, branch) conflicts
true
false
b1
b2
(b0, b3?b4)
x1
z1
(b1, b3?b5)
b3
if (x)
(b5, b6?b8)
true
false
b4
b5
y1
z2
(branch, branch) conflicts
(b0?b1, b6?b8)
b6
if (y)
(b0?b2, b6?b7)
true
false
b7
b8
z4
z3
b9
return z
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Infeasible Path Patterns
Type 1 emit/test signals
A1
Type 2 static scheduling (set and test on new
variables for context switching)
CUT1
0
1
A
B1
D1
0
1
CUT
0
1

B

C1
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Infeasible Path Patterns
Type 1 emit/test signals
1
0
A
Type 2 static scheduling
ltTerm,2gt

Type 3 Termination and preemption

Preemption
B1

Pause
ltTerm,1gt
Term
0
2
Check term. code
1

C1

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Infeasible Path Patterns
Type 1 emit/test signals
0
1
S1
Type 2 static scheduling
Type 3 Termination and preemption
A01
A11
S11
S10
Type 4 encode tick transitions using (s1,s2)
1
0
S2
B11
B01
S20
S21

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Eliminate Infeasible Path

• Conflicting pairs are easy-to-compute
• Cannot be directly encoded as ILP cons.
• (b0, b3?b4) ? N0E3?4 1 is wrong

b0
x0 if (y)

• (b0, b3?b4) is valid
• only if b1 is not executed

true
false
b1
b2
x1
z1
b3
if (x)
N0E3?4 - N1 1
true
false
b4
b5
y1
z2
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Encoding of Conflicting Pairs

• Find set S of basic blocks that invalidate a
  conflicting pair (bi,bj?bk)

WCET Analyzer
Program path analysis
C Binary
Micro-architectural modeling
ILP solver
WCET Critical path
ILP cons.
Inf. path detection
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Model-code Association
Esterel spec.
WCET Critical path
Esterel-IR node mapping
IR node-C line mapping
Esterel-BB mapping
C line-BB mapping
C code
C Binary
WCET analyzer
C compiler
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Performance Debugging
Esterel spec. L1 present A then L2 L3 L4
pause L100 present B then L101
L999 L1000
Estl. Stmts lists
Basic block counts
environment constraints
ILP constraints
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Experiment Setup
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Experimental Results
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Case Study Reflex Game
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Case Study Reflex Game

• READY STOP ? E35_36 E58_59 lt 1

Refined critical path!
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Conclusion

• Enabling software exec. of synch. language spec.
  on general-purpose processors
• Integrate static WCET analysis into synchronous
  specification based design flow
• Exploit infeasible path patterns in generated
  code for tighter WCET estimates
• Build and utilize specification-code associations
  for performance debugging at spec. level
• Provisional US patent filed (Aug. 2008)

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