Analysis of history effect in PD-SOI logic Gates

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Analysis of history effect in PD-SOI logic Gates

• FTFC, May 2003
• Vincent Liot, Philippe Flatresse

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OUTLINE

• Introduction
• PD-SOI MOSFET electrical behaviour
• History effect
• Logic gates characterization
• Accelerated History Effect method for
  non-monotonous Tp variations
• Inverter characterization, comparison with
  inverter chain
• Complex gates
• Conclusions

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PD-SOI device - electrical properties, Floating
body effect

• Fast process capacitive coupling
• Slow process Impact ionization, GIDL, Gate
  current, diodes currents
• Dynamic Vt in PD-SOI MOSFET Vt decreases with
  body charge

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Logic gates - inverter static state
1053mv at DC1
1180mv at DC0
64mv at DC1
416mv at DC0

• Body potential values depend on initial
  conditions
• DC0 body potential ? DC1 body potential ?
  different Propagation delays

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Logic gates Steady State, inverter case
Body potential (V)

• Steady State after DC1 condition Steady State
  after DC0 condition
• After 100000 to 1 million pulses logic gate
  Steady State needs specific algorithms
• DC0 body potential ? DC1 body potential ? SS body
  potential
• ? 3 different propagation delays

Inverter PMOS
1V
VB after DC1
VB at Steady State
VB after DC0
0
Inverter propagation delays
Inverter NMOS
Wn1um, Wp3,2um, F10MHz
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Logic gates propagation delay variations

• Delay variation can be higher than 10
• Best and worst cases gate delays can be
• At first transisitons after DC equilibrium
• At Steady State
• Between first transistions and steady state non
  monotonous propagation delay variations

Conclusion PD-SOI standard cells
characterization needs a specific methodology to
find best and worst cases
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Accelerated History Effect - Principle
Inverter PMOS
Quasi linear evolution
Fast body potential variation capacitive
couplings
Slow body potential deviation across one
period ?VB 1,5E-4 V
Inverter NMOS

• Body potential evoluates across one period with
  slow process
• The slow variation of body potential across one
  period is linear on a limited number of pulses
• Principle of the method measure slow body
  potential variation across one period and
  amplificate the slow variation

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Accelerated History Effect AHE NMOS subciruit

• 3 parts Measurement, charge injection and
  convergence control

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AHE Measurement of slow body variation
Voltage (V)
3E-5
?VB
Clock
0

• 2 voltage controlled voltage sources with delays
  allow the operation ?VBVB(t)-VB(t-période)
• VB(t) BI node, VB(t-période) Bold node

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AHE Charge injection
Voltage (V)
VB(t)
Charge injection
Bobj
Acc?VB
Bold VB(t-period)

• 1 voltage controlled voltage source allows the
  operation Bobj Bold Acc?VB
• Voltage controlled current source manage charge
  injection while VB(t)?Bobj during clock signal

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Accelerated history effect Body potential
accelerated evolution
NMOS Body potential (V)
NMOS Body potential (V)
Equivalent number of pulses
Number of simulated pulses

• NMOS body potential evolution 100 periods with
  Acc225, 25 periods with Acc900
• Body potential evolution with real time scale for
  different accelerations (112 to 900) shows
  accurate reproduction of circuit history

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Accelerated history effect Inverter delay
variation with different accelerations
Tp (ps)
Tp (ps)
Equivalent number of pulses
Number of simulated pulses

• AHE allows to simulate more than 100000 periods
  with a few tens of pulses

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AHE - validation at steady state
Number of cases
difference of Tp beetween AHE steady state
algorithm Harmonic Balance (Anacad)

• Inverter Wn1um, Wp3,2um, C5fF to 200fF,
  Slope10ps to 1000ps, VDD0,8V to 1,4V
• Less than 1 difference beetween AHE and SS
  algorithm
• ? Very accurate method

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Inverter History effect behaviour in
characterization space SlopeLoad
Fall history effect
Rise history effect
Cl (fF)
Cl (fF)
Slope (ps)
Slope (ps)

• Wn1um, Wp3,2um, F10MHz, VDD1,2V
• Maximum history effect at 5fF and 1000ps, 5-6 on
  falling transition, 10 on rising transition

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Inverter Non-monotonous variations
Tp Fall variation
Tp Fall variation
S1000ps
C5fF
Number of simulated pulses
Number of simulated pulses

• Wn1um, Wp3,2um, F10MHz, VDD1,2V
• NMOS evoluates much faster than PMOS
• Non-monotonous variations quikly reduce when S
  decrease or C increase

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Inverter Potential evolution and propagation
delay variations

• NMOS charge ? positive impact on TpFall, negative
  impact on TpRise
• PMOS charge ? negative impact on TpFall, positive
  impact on TpRise

• Fall transition of an invertig stage causes Rise
  transition on the next inverting stage
• Delay opposite variations induce history effect
  compensation gate per gate

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Inverter chain Delay variation
Tp (ps)
12,3ps 5,8
6,8ps 3,3
1,7ps 0,85
Number of simulated pulses

• Wn1um, Wp3,2um, S500ps, C10fF, F10MHz

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Inverter Chain Gate per gate history effect
Tp Rise variation
Tp Fall variation
Number of simulated pulses
Number of simulated pulses

• Wn1um, Wp3,2um, S500ps, C10fF, F10MHz
• Negligible non-monotonous delay variations on
  three inverter chain, history effect decreases
  with number of gates

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History effect in standard cells
Inverseur 1 stage
NAND2 1 stage, 2 stacked NMOS
NOR3 1 stage 3 stacked PMOS
OR3 2 stages, 3 stacked PMOS
MUX21  2 stages, pass gates
XOR  3 stages, pass gates
Latch  3 stages, pass gates
Flip-Flop  4 stages, pass gates
3 inverters chain Slope 500ps Load 10fF

• History effect decreases as gate complexity
  increases
• Slope reduction through the gate
• Increased capacitance

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Conclusion

• AHE method developped to characterize
  non-monotonous history effect
• Valid whatever the partially depleted SOI logic
  gates
• Technology and Spice simulators independent
• History effect
• history effects are reduced for slow input slope
  and large load capacitances
• Carefull design reduces history effect Low
  power design means fast input slopes
• Non-monotonous variations can be neglected due to
  gate to gate compensation effect
• Complex gates
• History effect is reduced through in gates
  including a large number of stages and/or load
  capacitances

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AHE - method improvement
End of transistor accelerated evolution, signal
for next acceleration

• Problem NMOS evoluates much faster than PMOS
• Calculation of Acc and automatisation of
  acceleration switch allows large gates
  characterization