Chapter 6 -- Introduction to Sequential Devices

1
Chapter 6 -- Introduction to Sequential Devices
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The Sequential Circuit Model
Figure 6.1
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State Tables and State Diagrams
Figure 6.2
4
Sequential Circuit Example
Figure 6.3
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TTL Memory Elements
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SR Latch Characteristics
Figure 6.11 Q S R?Q
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Latch and Flip-flop Timing
Figure 6.4
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Set Latch
Figure 6.5
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Reset Latch
Figure 6.6
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Set-Reset Latch (SR latch)
Figure 6.7
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NAND SR Latch
Figure 6.8
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Set-Reset Latch Timing Diagram
Figure 6.9
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SR Latch Propagation Delays
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SN74279 Latch with Two Set Inputs
Figure 6.12
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Gated SR Latch
Figure 6.13
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Gated SR Latch Characteristics
Figure 6.14 Q SC R?Q C? Q
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Delay Latch (D latch)
Figure 6.15
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D Latch Characteristics
Figure 6.16 Q DC C?Q
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D Latch Timing Diagram
Figure 6.17
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D Latch Timing Constraints
Figure 6.18
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Pulse-Triggered JK Flip-Flop Characteristics
Figure 6.25 Q K?Q JQ?
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Pulse-Triggered JK Flip Realization
Figure 6.26
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The SN7476 Dual Pulse-Triggered JK Flip-Flop
Figure 6.27
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SN7474 Dual Positive-Edge-Triggered D Flip-Flop
Figure 6.28
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SN7474 Excitation Table
Figure 6.29
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SN7474 Flip-Flop Timing Specifications
Figure 6.30
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Summary of Latch and Flip-Flop Characteristics