UNIFIED ARCHITECTURE SPECIFICATION

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UNIFIED ARCHITECTURE SPECIFICATION

• SUPERVISED BY
• Prof. M. BALAKRISHNAN
• BTP Part-I PRESENTATION
• PRESENTED BY
• KAUSHAL SHUBHANK
• SUMIT KUMAR

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SoC Challenge

• Aim is to exploit the configurability and
  customizability offered by the system-on-chip
  approach.
• Most of SoC Applications offer good amount of
  functional and data parallelism.
• Architecture customization leads to design
  solutions which are cheaper.
• Application Specific Instruction Processors
  (ASIPs) are important components of SoCs.
• SRIJAN explores application specific,
  heterogeneous, ASIP (VLIW and RISC) based
  multiprocessor System on Chip at both system as
  well as subsystem level.

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SRIJAN Simulator Flow
SystemC (.cc files)
Application
MDES (hmdes, CFG)
Execution Profile
COMPONENT LIBRARY
USER_PARMS (no. of regs.)
IMPACT
Loads Memory Images and runs
Makefile (executable Is formed)
Simulator
Temporary assembly files (created in workspace)
Makefile_srec
Memory Images (.srec)
UNIP
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Original procedure for architecture exploration

• Change the MDES description in the Synthesis part
  and generate memory images by compiling the
  application.
• Change the SystemC description in the Simulator
  part and generate the executable.
• The simulator loads the memory images and
  generates the execution profile by running the
  executable.

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Problems with SRIJAN

• Mdes and SystemC formats need to be compatible
  with each other for any simulation to run.
• Forces the need for user to have fair bit of
  knowledge about the two formats of architecture
  descriptions and working of Srijan Simulator.
• Very few changes were supported originally.
• Less user friendly because of the complex
  directory arrangement.

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Aim

• Automate the procedure of architecture
  exploration.
• Support more changes to enhance domain of
  architecture exploration.
• Validate energy values generated by the
  simulator by comparing with those generated by
  RTL description.
• Make the framework more user friendly.

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MDES Architecture Description

• The High Level Machine Description Facility - the
  machine description language used in Trimaran.
• Describes a processor architecture from the
  compiler's point of view. Specifies the
  instruction format, resource usages and
  reservation tables, latency information,
  operation information and some compiler specific
  information.
• The instruction format conveys what operands are
  allowed by each type of operation.
• Resource usages specify how operations use
  processors.
• Latency information specifies how to calculate
  dependence distances between operations.
• Finally, operation information specifies the
  operations supported by the architecture.

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SYSTEMC Architecture Description

• SystemC is a C based standard for specifying
  hardware/software systems at various levels of
  abstraction system level, behavioural level, and
  register transfer level.
• SystemC model when compiled with C compiler
  forms the executable representing the simulator.
• Memory, CSS (Communication Sub-system), Cache and
  Processor are modeled using SystemC and are parts
  of the Component Library.
• Components connected through another architecture
  description file to compose architecture.

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VHDL architecture description

• Memory, CSS (Communication Sub-system), Cache and
  Processor are modeled using VHDL and then
  composed to form the architecture.
• Used to generate energy values by using
  Instruction Energy Library.
• This library has been generated keeping in mind
  inter Inst. Energy dependence requirements.
• Any change in architecture leads to change in
  energy statistics.

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Modified Simulator Flow
Original Flow
Parameters
Mdes files
Parser
Unip
Makefile
SystemC files
User_parms
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Changes supported

• Number of Registers
• Issue Slots
• Latencies for different operations
• Bypass
• DMSS Ports
• Slot wise distribution of operations

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numreg 64 // Must be greater than 16 Islots 4 //
Must be less than 8 and ofcourse a power of 2
Bypass 1 // 1 indicates true and 0 indicates
false /Common Parameters / LatIMul 2 //
LatIDiv 3 // LatFAddsub 2 // LatFConv 2 //
LatFMul 3 // LatFDiv 2 // LatLoad 2 // Can't
be changed /Latency Values / NumDMSSports 4 //
Must be greater than or equal to Issue slots
/SYSTEMC Parameters / LatFAlu 2 // MAX_LAT 4
// must be 1 max(all latencies) /MDES
Parameters / CmpSlots 0 1 2 3 // don't go
beyond issue slots-1 ShiftSlots 0 1 2 3 //
don't go beyond issue slots-1 LdStSlots 0 1 2
3 // don't go beyond issue slots-1 CMemSlot 3
// must be one of LdStSlots IAluSlots 0 1 2 3
// don't go beyond issue slots-1 IMulSlots 0 1
2 3 // don't go beyond issue slots-1 FAluSlots
2 // don't go beyond issue slots-1 FConvSlots
1 // don't go beyond issue slots-1 FMulSlots
1 // don't go beyond issue slots-1 IDivSlots
1 // don't go beyond issue slots-1 FDivSlots
0 // don't go beyond issue slots-1 /Functional
Units /
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Modified procedure for architecture exploration

• Change the user_parms file (shown earlier)
  keeping in mind the limitations specified.
• Generate the executable for the desired
  application.
• Simulate to get the execution profile along with
  energy statistics.

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Some Results

• Five Applications used for testing.
• Default Settings used are
• Num_reg -gt64
• Issue Slots/DMSS Ports -gt4
• Bypass -gt True
• Nine different architectures used for comparing
  execution cycles by varying the no. of Issue
  Slots and registers.

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Performance Comparison
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Future Work
Parameters
Execution Energy Profile
MDES
TOOL
Srijan Simulator
SystemC
RTL
Inst Energy Lib
Validation ??
NETLIST
Gate Level Simulator
Execution Energy Profile
Test Bench (Program Data Memory)
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Target for next semester

• Integration of some kind of intelligent tool with
  Srijan Framework which can help the designer in
  narrowing down his design choices by looking at
  application and some initial simulation results,
  guiding him to the best architecture.
• Designing a Web Interface to make the framework
  more user friendly and allow simulation to be
  carried out on Windows as well.

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REFERENCES

• Srijan Progress Reports June 2004 - May 2005,
  Nov 2003 May 2004 and Nov, 2002 March 2003.
• A Trimaran Based Framework for Exploring the
  Design Space of VLIW ASIPs with Coarse Grain
  Functional Units Bhuwan Midha, Varun Raj, Anup
  Gangwar, M.Balakrishnan, Anshul Kumar, and Paolo
  Ienne.
• SrijanSim A Retargetable And Efficient System
  Simulation Framework B.Tech Report by Abhishek
  Marwah and Gaurav Bansal, 2004.
• Mdes Manuals and HPL-PD manuals (available under
  documentation of Srijan Project).
• John Christopher Gyllenhaal, A machine
  description language for Compilation University
  of Arizona, 1991.
• Reports of past projects carried out under the
  Srijan Methodology available at the official
  website of Embedded group, IIT Delhi.