DOR

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DOR

• DOM Readout card
• Status Report, October 2003
• K.-H. Sulanke

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Contents

• DOR card
• Firmware Status
• Production Status, Rev. 0
• Planned Production, Rev. 1

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DOR, Block Diagram
Reload
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DOR, DOM Readout card
96V DOM Power
Quad Cable Con.
Power Switch
Comm. DAC
Clock Time String port
Comm. ADC
PLD
Comm. Rec.
FPGA
FLASH
SRAM
JTAG
ICECUBE Meeting, Mons October 2003
11/18/2009
K.-H. Sulanke, DESY Zeuthen
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DOR Rev. 0, Main Firmware Status

• PCI Bus control including DMA (..120 MB/s)
  Interrupts
• In system firmware update by Software
• Parallel control of 2 wire pairs / 4 DOMs
• 1MBit/s serial data rate, (50KB per DOM)
• DOM_a/b polling
• Automatic cable length adaption
• Software initiated but firmware controlled time
  calibration
• Three running firmware versions
• DOR_TEST, after production test
• vDOM, includes two virtual DOMs for Linux driver
  test
• DOR, final version, under development

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Production Status

• Rev. 0, 10 DORs running at UW 2x, Bartol 1x,
  LBNL 7x
• 20 more in production now, ready in Dec. 2003
• 4 stay at DESY, 16 go to ?

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Planned Production, Rev. 1

• Redesign ready in January
• first test in Feb., production of 60 if o.k.
• 60 ready in April 2004
• 60 DORs -gt sufficient to control 480 DOMs

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DOM Hub
ICECUBE Meeting, Laguna Beach March 2003
11/18/2009
K.-H. Sulanke, DESY Zeuthen
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