ResistiveOpen Defect Injection in SRAM CoreCell: Analysis and Comparison between 0'13m and 90nm Tech

1
Resistive-Open Defect Injection in
SRAMCore-Cell Analysis and Comparisonbetween
0.13µm and 90nm Technologies
42nd Design Automation Conference Anaheim
Convention Center, Anaheim, USA, June 13-17, 2005
M. Bastian
L. Dilillo P. Girard S. Pravossoudovitch
A. Virazel
ASSOCIATE A503
2
Outline

• Introduction
• Robustness of the core-cell
• Dynamic fault sensitivity of the core-cell
• Test procedure
• Conclusion Perspectives

3
1. Introduction - context
ITRS roadmap

• Memories concentrate defects
• Memories advanced technologies
• Development of efficient test solutions

4
1. Introduction problem statement

• Static faults in SRAM
• Stuck-at, Transition, Coupling, etc.
• March tests are efficient for static fault
  detection

4
5
1. Introduction - purpose

• Analysis of resistive-opens in the SRAM core-cell
• Comparison between 130nm and 90nm Infineon
  technologies
• Robustness
• Dynamic fault sensitivity
• New March-based test solution
• A unique Test procedure
• Complete coverage of all dynamic faults for both
  technologies

6
2. Robustness - simulation flow
BLB
BL
WLS
Vdd
Mtp2
SB
Mtn2
Mtn4
Mtn3
Vdd
Mtp1
S
Mtn1
Resistive open defects in the SRAM core-cell
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2. Robustness - simulation flow

• Electrical simulations / Test conditions
• Infineon internal SPICE-like simulator
• Resistance values range from 1O to 100 MO
• Similar simulation conditions for both
  technologies
• Process corner (TYPICAL)
• Temperature (27C)
• Supply Voltage (1.5V for the 130nm, 1.2V for the
  90nm)
• Active mode (functional mode)

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2. Robustness - simulation results
Minimumresistance
Defect
Technology
Fault model
0.13 µm
TF
25 kO
Df1
90 nm
TF
200 kO
0.13 µm
RDF
20 kO
Df2
90 nm
RDF
1 MO
0.13 µm
RDF
7 kO
Df3
90 nm
RDF
500 kO
0.13 µm
dRDF
16 MO
Df4
90 nm
dRDF
50 MO
0.13 µm
TF
200 kO
Df5
90 nm
TF
10 MO
0.13 µm
TF
2 MO
Df6
90 nm
TF
3 MO
dRDF Dynamic Read Destructive Fault
TF Transition FaultRDF Read Destructive Fault
? same fault models extracted for both
technologies
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2. Robustness - simulation results
? difference in terms of robustness
In presence of resistive-open defects, the 90 nm
core-cell is more robust than the 130 nm
A higher supply voltage (in 130 nm) makes the
memory surprisingly less stable
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3. Dynamic fault sensitivity
All different operation conditions (P,V,T) have
now been considered
DRDF Deceptive Read Destructive Fault
IRF Incorrect Read Fault
? different fault models extracted for defects
Df2 and Df3
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3. Dynamic fault sensitivity
The dynamic behavior (dRDF 90nm) is obtained
when

• Defect Df2
• Active mode (functional mode)
• Process typical
• Supply voltage 0.8 V
• Temperature - 40C
• Slow mode (low power)
• Any PVT conditions
• Defect Df3
• Active mode (functional mode)
• Process typical
• Supply voltage any value
• Temperature - 40C
• Slow mode (low power)
• Process typical
• Supply voltage any value
• Temperature - 40C

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3. Dynamic fault sensitivity
BLB
BL
Ex dRDF induced by Df2 in the 90nm core-cell
WLS
Vdd
Mtp2
Df2
SB
Mtn2
S
Mtn4
Mtn3
Vdd
Mtp1
Mtn1
950 kO, slow mode, typical process, 1.2V, 27C
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3. Dynamic fault sensitivity
BLB
BL
Ex dRDF induced by Df2 in the 90nm core-cell
WLS
Vdd
0
1
Mtp2
Df2
SB
Mtn2
S
10
Mtn4
Mtn3
Vdd
01

CLK

Mtp1
DO

Mtn1

w1
SB






A 1 is written in the cell ? Node SB goes to
0.
950 kO, slow mode, typical process, 1.2V, 27C
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3. Dynamic fault sensitivity
BLB
BL
Ex dRDF induced by Df2 in the 90nm core-cell
WLS
Vdd
Mtp2
Df2
SB
Mtn2
Mtn4
Mtn3
Vdd

CLK

Mtp1
S
DO

Mtn1
w1

r1
SB






First read operation ? degradation of the node
level due to Df2
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3. Dynamic fault sensitivity
BLB
BL
Ex dRDF induced by Df2 in the 90nm core-cell
WLS
Vdd
Mtp2
Df2
SB
Mtn2
Mtn4
Mtn3
Vdd

CLK

Mtp1
S
DO

Mtn1
w1

r1
r1
r1
SB






Additional read operations ? faulty swap of the
cell after three consecutive read
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3. Dynamic fault sensitivity
Impact of the resistance value Df2 and Df3
130 nm core-cell
Fault-free cell
RDF
TF
Resistance (O)
0
20 kO (Df2) 7 kO (Df3)
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4. Test procedure

• Static fault detection
• Stuck-at, TF, CF, RDF and DRDF
• March tests like MATS, March C-, March C

? These tests are not able to cover the dynamic
RDFinduced by Df2, Df3 (90nm only) or Df4 !!!!
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4. Test procedure

• Dynamic fault detection
• dRDF detection requires
• Read after write
• Multiple read operations
• RAW test algorithm (w0r0 / w1r1) not sufficient
• Read Equivalent Stress
• A read or write operation on a cell involves a
  stress equivalent to a read operation on the
  other cells of the same word line

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4. Test procedure - RES
BL0
BLB0
BL1
BLB1
BL2
BLB2
BL3
BLB3
BL4
BLB4
BL5
BLB5
WLi-1
WLi
Ci,0
Ci,1
Ci,2
Ci,3
Ci,4
Ci,5
WLi1
Part of a SRAM cell array
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4. Test procedure - RES
Precharge on (Vdd)
BL0
BLB0
BL1
BLB1
BL2
BLB2
BL3
BLB3
BL4
BLB4
BL5
BLB5
WLi-1
WLi
Ci,0
Ci,1
Ci,2
Ci,3
Ci,4
Ci,5
WLi1
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4. Test procedure - RES
Precharge on (Vdd)
Precharge off (floating Vdd)
BL0
BLB0
BL1
BLB1
BL2
BLB2
BL3
BLB3
BL4
BLB4
BL5
BLB5
WLi-1
WLi
Ci,0
Ci,1
Ci,2
Ci,3
Ci,4
Ci,5
WLi1
When a cell is selected for a r/w operation the
precharge circuit is normally turned OFF on its
bit lines, for the others it is left ON
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4. March Test Solution - RES

• a. Faulty cell w0 r0 r0

SB
a
S
r

0 (

c

a

s

e

a

)

r

0 (

c

a

s

e



a

)

w

0

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4. March Test Solution - RES
a. Faulty cell w0 r0 r0 b. Faulty cell
w0 Read operations on the other cells ? RES
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4. Test procedure - Algorithm

• Test requirements lt1, w0-RESn, r0 gt
• Elements have to include w0 (sensitization)

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4. Test procedure - Algorithm

• Test requirements lt1, w0-RESn, r0 gt
• Elements have to include w0 (sensitization)
• RESn ? Address sequence word line after word line

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4. Test procedure - Algorithm

• Test requirements lt1, w0-RESn, r0 gt
• Elements have to include w0 (sensitization)
• RESn ? Address sequence word line after word
  line
• Elements have to include r0 (observation)

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4. Test procedure - Algorithm

• Test requirements lt1, w0-RESn, r0 gt
• Elements have to include w0 (sensitization)
• RESn ? Address sequence word line after word
  line
• Elements have to include r0 (observation)
• Additional elements ltw1-RESn, r1gt symmetrically
  located defects

BLB
BL
WLS
Vdd
Mtp2
Df2
SB
Mtn2
S
Mtn4
Mtn3
Vdd
Mtp1
Mtn1
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4. Test procedure - Algorithm

• Test requirements lt1, w0-RESn, r0 gt
• Elements have to include w0 (sensitization)
• RESn ? Address sequence word line after word
  line
• Elements have to include r0 (observation)
• Additional elements ltw1-RESn, r1gt symmetrically
  located defects
• All the (sensitization) elements performed in
  both ? and ? orders

RESmax
RESmin
RESmax
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4. Test procedure - Algorithm
MARCH C-

• March C- without RES covers 0 of dRDF
• March C- with RES covers 100 of dRDF
• Single modification - address sequence word line
  after word line is allowed by the 1st of the
  six degrees of freedom of March tests.
• New March C- still detect the former target
  faults (TF, IRF, DRDF)

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5. Conclusion Perspectives

• Analysis of resistive-opens in the SRAM core-cell
• Comparison between 130nm and 90nm technologies
• Higher robustness of the 90nm core-cell
• Higher dynamic fault sensitivity of the 90nm
  core-cell
• New March-based test solution
• A unique test procedure based on the RES concept
• March C- with a particular addressing sequence
• Complete coverage of all extracted fault models
  for both techno.
• Low (linear) complexity 10N
• Perspectives
• Dynamic faults in other parts of the SRAM
  (pre-charge, sense amplifier, write driver, )