ELECTRON LOGIC LIGHT CHAPTER 3 3.13.4 3.5.13.5.2, 3.5.6, 3.5.7 3.6.13.6.2 3.7.13.7.4 3.10

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ELECTRON LOGIC LIGHT CHAPTER
33.1-3.43.5.1-3.5.2, 3.5.6, 3.5.73.6.1-3.6.23.
7.1-3.7.43.10
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SEMICONDUCTORS
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IC PRODUCTION
Materials Wafers Chips Packages Boar
ds
Appliances
 
 
 
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Si ? iP
Si mask (close-up) wafer
chips Pentium 4 router scale
DIPs (MSI) mother board iPhone
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LITHOGRAPHY
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• But what is inside?
• How does it work?

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TODAY

• Computing Boolean expressions with solid state
  circuits
  
• Very Large Scale Integration with
• Complementary Metal-Oxide
• Semiconductor Field Effect Transistors.
• (VLSI with C MOS FET)

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WHY DIGITAL?

• Analog values are impossible to reproduce
  exactly.
  
• Instead of manipulating an analog value, use
  digital logic
  
• 47 ? 00101111
• Digital circuits give the same interpretation
  to a whole range of analog values.
  
• e.g.
• 4 V ? 1
• 2-4 V ? ?
• A/D circuits can converts an analog value like 47
  to eight digital signals in the range 0-2 and
  4-5 volts.

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Digital logic

• Digital logic allows precise and repeatable
  manipulation
  
• Add or multiply - x /
• Compare
• Store
• Transmit

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Is it really analog or digital?
5 Volt positive logic
tape faulty !
0.1V
AND
OR
EJECT
4.4V
4.9V
4.1V
0.7 V
OK
4.2 V
Eject
EJECT (X and Y) or Z
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Digital Circuit Jargon

• Source, Drain of charge carriers
• n-channel, p-channel doping with extra charge
  carriers
  
• Gate (1) AND, NOR
• Gate (2) region between Source and Drain
• Device type e.g. bipolar junction transistor
• Logic family collection of compatible devices
  like 5V TTL
  
• High, Low logic voltage ranges
• Positive / Negative logic 1 higher/lower
  voltage than 0
  
• Assert, Negate apply appropriate voltage

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ACTIVE ELEMENTS

• Transistors come in two types, many families and
  two genders
  
• Bipolar junction transistors BJT ? TTL logic
• NPN and PNP (pnp is seldom used it needs
  voltage source)
  
• Metal-oxide semiconductor field-effect
  transistors
  
• (MOSFET or MOS) ? CMOS (complementary) logic
• NMOS and PMOS (n-channel and p-channel)
• We consider only positive logic (1 is HIGH, 0 is
  LOW) voltage

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Metal-oxide-semiconductor field-effect transistor
(magnified 3.4 zillion times)
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CMOSCOMPLEMENTARY SWITCHES

• CMOS transistors are almost always married and
  appear in pairs.
  
• One is on (conducting) and the other is off
  (open).
  
• This reduces voltage and current fluctuations
  elsewhere.
  
• They act like a voltage-controlled switch
• (or, more exactly, like a voltage-controlled
  resistor that has either a very high resistance
  (several Megohms) or very low resistance (Kohm).
• When they are on, the current flows from source
  to drain or vice-versa.
  
• The control voltage is applied to the base, which
  is insulated,
  
• so no current flows into or from the base (field
  effect!).
  
• CMOS devices have 3 terminals.

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A CMOS couple

• The arrows always point from positive to
  negative, because that is the way the current
  flows.

NMOS
PMOS
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ORIENTATION in CIRCUIT
5 V
PMOS NMOS
0 V
OK NEVER SELDOM
Arrow indicates that current flows from V to 0.
You can flip the gates left to right, but not
upside down
(like a mirror).
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PMOS and NMOS
In NMOS, electron flow in the channel is
enhanced when the gate is HIGH (near V) with
respect H to the source the gate is ON.
In PMOS, electron flow in the channel is
enhancedwhen the gate is LOW (near 0V) with
respect to the source the gate is ON.
L
These symbols sidestep the orientation issue!
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INVERTER with a CMOS couple
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Equivalent voltage-controlled switch
a mechanical swith analog


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Inverter with bubble symbol
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Inverter with bubble symbol
H
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CMOS NAND gate
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CMOS NAND gate
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CMOS NAND gate
H
L
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CMOS-NAND equivalent switch model
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Back-of-envelope analysis of CMOS gates
B
A
output
A
prime the bubbles!
B
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Back-of-envelope analysis of CMOS gates
A L
B H
output
A H
Transistor is on iff its input is high.
Here the output is connected to V, and not
connected to ground, so it is high.
Q next!
B L
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QUIZ ! Fill out Table (b) and give circuit symbol
Q3
Q4
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QUIZ SOLUTION
on off off on on off off on
Q3
Q4
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NOR gate (it is like an upside-down NAND gate)
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3-input NAND gate(What would a 4-input NAND gate
look like?)
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Yes, but look at the 8-input CMOS NAND gate
Fan-out limitation
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More detailed circuit analysis (3.4)

• Static and dynamic characteristicsLogic voltage
  levelsFanoutDC noise marginsSpeedPower
  consumptionNoise (cosmic rays, power supply, mag
  fields, )Electrostatic dischargeOpen-drain
  outputThree-state outputs

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Noise Margin
Noise margin is the maximum voltage that can be
added to or subtracted from the logic voltages
and still have the circuit interpret the voltage
as the correct logic value.
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CMOS Inverter I/O Transfer Characteristics
Vout 5V 4.0 V
Hign noise margin 4.0 - 3.5 0.5V
Low noise margin 2.5 - 0.8 1.7V.
0.8 V
Vin 5V
0 0
2.5 V 3.5V
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Quiz
If anything below 2V is considered 0,
and anything above 3V is considered 1,
what is the noise margin of this idealized
inverter? Can we increase the noise margin by
setting a different threshold for 0 and 1?
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Solution
If anything below 2V is considered 0,
and anything above 3V is considered 1,
what is the noise margin of this idealized
(and symmetric) inverter? Vin 3V ? Vout 5/3
V Margin 2 - 5/3 1/3 V 10/3 - 3 Can we i
ncrease the noise margin by setting a different
threshold for 0 and 1? Yes! 4V
? 1 Margin 1 0 1 V 5 - 4
Vout -5/3 Vin 20/3
10/3 5/3
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Noise Margin
Noise margin is the maximum voltage that can be
added to or subtracted from the logic voltages
and still have the circuit interpret the voltage
as the correct logic value.
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Noise Margin for an Inverter
Noise margin is the maximum voltage that can be
added to or subtracted from the logic voltages
and still have the circuit interpret the voltage
as the correct logic value.
logic high
logic high
logic low
logic low
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Vout a x Vin b 0 a x 4 b 5 a x 1
b
Vout - 5/3 Vin 20/3 (eqn 1)
(A) Max Vin_0 2V (given) ? Min Vout_1 10/3
V (eqn 1) Min Vin_1 3V (given) ? Max Vout_0
5/3 V (eqn 1) High Noise Margin Min Vout
Min Vin 10/3 3 1/3 V
Low Noise Margin Max Vin Max Vout 2
5/3 1/3 V
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Vout - 5/3 Vin 20/3 (eqn 1)
(B) Max Vin_0 1V ? Min Vout_1 5 V (eqn 1)
Min Vin_1 4V ? Max Vout_0 0 V (eqn 1)
High Noise Margin Min Vout Min Vin 5 -
4 1 V Low Noise Margin Max Vin Max Vout
1 - 0 1 V Better !
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Load effects need Thevenin equivalent

• Equivalent R resistance of looking into output
  terminals with voltages set to 0 (i.e., two
  resistors in parallel)
  
• Equivalent V output voltage with open
  terminals(i.e., a voltage divider).

Leon Charles Thevenin (1857-1926) was a French
telegraph engineer.
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THEVENIN EQUIVALENT CIRCUIT
Rt resistance looking into output terminals
with all sources shorted. Vt no-load voltage at
output terminals
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Load effects Thevenin equivalent circuit of a
CMOS inverter with a resistive load
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Equivalent circuit with HIGH input
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Equivalent circuit with LOW input
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Propagation Delay
There is a lag between an input change and the
corresponding output change. Propagation delay
refers to the amount of time needed for a change
in the input signal to produce a change in the
output signal.
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Transition time

• CMOS devices take longer to turn on than to turn
  off
  
• (like old men).
• In families, the PMOS devices are larger than the
  NMOS to make the make the timing symmetrical.

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Some ballpark numbers

• Vcc 5V
• High output 3.0 V
• Low output
• Dynamic power dissipation 1.0 mw
• Static power dissipation 0.1 mw
• Propagation delay 5 ns
• Speed-power product 3 picojoules at 10 Mhz
• (propagation delay x power consumption of gate)
• At current speeds, capacitive and inductive
  effects dominate
  

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Some other devices (3.7)

• Three-state buffer
• Open-drain driver
• Junction transistor

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Three-state buffer (e.g., for a )
PCMCIA card to Controller Area Network (CAN)
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Hi Impedance

• R resistance
• Z impedance
• resistance plus capacitance or
• resistance plus inductance
• (in circuit analysis, usually represented
• by a complex number z a jb)
• Hi-Z means that very little current flows

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Open-drain CMOS NAND gate for driving LEDs
Ugh!
Hi-Z
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OPEN-DRAIN LED DRIVER
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Inverter with a junction transistor(logic NOT
complementary!)
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Alphabet Soup

• HC, HCT, AHC, AHCT, AC, ACT, FCT, FCT-T, LVCMOS,
  TTL, LVTTL, ECL, BiCMOS,
  
• (Advanced, Highspeed, Fast, LowVoltage,Ttlcompatib
  le, EmitterCoupled, BipolarCmos,)
  
• Families differ in
• speed, source voltage, power-dissipation,
  fan-in, fan-out, CMOS-TTL compatibility.
  
• Device numbers are usually the same, regardless
  of circuit family (cf. next chapter).

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Family differences
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SUMMARY

• Digital circuits are analog circuits which treat
  their inputs and outputs as equivalent to 0 or 1
  over a wide range of voltage.
  
• CMOS circuits work in pairs. Depending on whether
  the input voltage at the base is high or low,
  they establish a low-resistance path from the
  supply voltage (say 5V) or from ground ()V) to
  their output, and a high-resistance path to the
  other.
• Their behavior can be analyzed by observing which
  transistors are on and which are off for a every
  possible H and L combination of inputs.
  
• CMOS NAND and NOR gates have at least 4, and 2
  more for every additional input.
  
• Some digital logic circuits have floating
  (high-Z) outputs.
  
• Junction transistors are controlled by current to
  the base(indirectly, voltage). Some can be
  combined with CMOS.
  

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Next VHDL!

• Read 5.1 5.3 in Wakerly and
• Chapter 9 in LogicWorks 5
• Skip ABEL and VERILOG examples.