Computer System Overview

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Computer System Overview

• Chapter 1

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Computer components

• Processor (CPU)
• Main Memory (RAM, primary memory)
• volatile, store data and program
• I/O modules
• secondary memory devices, communications
  equipment, terminals
• System interconnection (bus)
• communication among processors, memory, and I/O
  modules

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Computer components
CPU
PC
I/O AR
IR
I/O BR
MAR
MBR
Bus, System interconnection
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Internal registers

• What is register?
• PC - Program Counter
• IR - Instruction Register
• MAR - Memory Address Register
• MBR - Memory Buffer Register
• I/OAR - I/O Address Register
• I/OBR - I/O Buffer Register

Usually, most of these registers are not directly
visible to system programmers.
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Reading/writing Memory
RAM
CPU
00000
MAR
00001
123
MBR
00002
26
00003
00004
00005
.
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User-visible registers (1/2)

• Data registers - for calculation.
• Enable programmer to minimize main memory
  references by optimizing register use.
• Address registers
• contain main memory address of data and
  instructions
• may contain a portion of an address used to
  calculate the complete address

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User-visible registers (2/2)

• Program Status Word (PSW)
• condition codes/flags - Bits set by the processor
  hardware as a result of operations
• Examples positive, negative, zero, overflow
• many other control bits, e.g. interrupt
  enable/disable, supervisor mode

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Instruction Cycle

• Instructions are fetched from memory one at a
  time
• The fetched instruction is then executed by the
  processor

Fetch Stage
Execute Stage
Fetch Next Instruction
Execute Instruction
START
HALT
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Instruction Fetch

• Program counter (PC) holds address of the
  instruction to be fetched next
• The processor fetches the instruction from memory
  to the Instruction register (IR)
• Program counter is incremented after each fetch

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Categories of Instructions

• Processor-memory transfer data between processor
  and memory
• Processor-I/O transfer data between processor
  and I/O module
• Data processing perform arithmetic or logic
  operation on data
• Control change the sequence of execution

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Instruction Execution
RAM
CPU
00000
PC
The CPU executes the instruction pointed by PC,
one after another.
00001
MOV AX, 00009
IR
00002
INC AX
00003
AX
MOV 00009, AX
How can it handle I/O and multiprogramming?
00004
GOTO 00001
00005
.
0
00009
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Interrupt

• An interruption of the normal processing of
  processor
• Classes of interrupts
• Program, e.g. arithmetic overflow, division by
  zero, execute illegal instruction, reference
  outside users memory space
• Timer
• I/O (Why interrupt?)
• Hardware failure

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Transfer of Control via Interrupts
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Instruction Cycle with Interrupt
Fetch Stage
Execute Stage
Interrupt Stage
Fetch next instruction
Execute instruction
Check for interruptExecute interrupt handler
START
Interrupt enabled
HALT
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Interrupt Stage

• Processor checks for interrupts
• If no interrupts fetch the next instruction for
  the current program
• If an interrupt is pending, suspend execution of
  the current program, and execute the interrupt
  handler

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Interrupt Handler

• A program that determines nature of the interrupt
  and performs whatever actions are needed
• When the CPU is interrupted, control is
  transferred to this program
• When finished, control is transferred back to the
  program interrupted
• Generally part of the operating system

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Program Flow of Control Without Interrupts
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Program Flow of Control With Interrupts, Short
I/O Wait
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Program Flow of Control With Interrupts Long I/O
Wait
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Multiple Interrupts, Sequential Order

• Disable interrupts while an interrupt is being
  processed
• Interrupts remain pending until the processor
  enables interrupts
• After interrupt handler routine completes, the
  processor checks for additional interrupts

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Sequential Interrupt Processing
Interrupt Y occurs
Interrupt X occurs
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Multiple Interrupts, Priorities

• Higher priority interrupts cause lower-priority
  interrupts to wait
• Causes a lower-priority interrupt handler to be
  interrupted
• Example when input arrives from communication
  line, it needs to be absorbed quickly to make
  room for more input

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Multiple Interrupts, Priorities
Interrupt Y occurs, which has higher priority
Interrupt X occurs
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Multiple Interrupts
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Memory Hierarchy
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Going down the Hierarchy

• Decreasing cost per bit
• Increasing capacity
• Increasing access time
• Decreasing frequency of access of the memory by
  the processor

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Disk Cache

• A portion of main memory used as a buffer to
  temporarily hold data for the disk
• Disk writes are clustered
• Some data written out may be referenced again.
  The data are retrieved rapidly from the software
  cache instead of slowly from disk

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Cache Memory

• Processor speed is faster than memory speed
• Invisible to operating system
• Increase the speed of memory
• Small caches have a significant impact on
  performance

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Cache Memory (how it works)

• Contains a portion of main memory
• Processor first checks cache
• If not found in cache, the block of memory
  containing the needed information is moved to the
  cache

Locality of reference During the course of
execution of a program, memory references by the
processor, for both instructions and data, tend
to cluster.
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I/O Communication Techniques

• Programmed I/O
• Interrupt-driven I/O
• Direct Memory Access (DMA)

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I/O Communication Techniques
Some data on harddisk
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Programmed I/O

• No interrupts occur
• Processor is kept busy checking status

I/O are much slower than the CPU. It is very
inefficient for the CPU to wait for I/O
completion in a tight loop. (busy waiting).
More on this in later chapters.
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Programmed I/O
procedure readString (var s) repeat Send I/O
command go read a word repeat Read I/O
status until I/O done Read word from I/O
module Write word into memory until finished
reading
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Interrupt-Driven I/O

• No busy waiting. Processor can proceed to do
  other things when I/O is in progress
• When I/O is done, the CPU is interrupted

Still consumes a lot of processor time because
every word read or written passes through the
processor
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Interrupt-Driven I/O
procedure readString (var s) repeat Send I/O
command go read a word now, the CPU
will do something else dont bother checking
I/O status until finished reading
When the I/O module finished reading the word, it
interrupts the CPU. The CPU will execute an
interrupt handler to move the word to memory.
/ interrupt handler / Read word from I/O
module Write word into memory return
Afterwards, control is returned to the program
which continues to read the next word.
Interrupt-driven I/O is still inefficient in data
transfer of large amount because the CPU has to
transfer the data word by word between I/O module
and memory.
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Direct Memory Access

• Processor grants I/O module authority to read
  from or write to memory
• DMA module controls exchange of data between main
  memory and the I/O device
• Processor interrupted only after entire block has
  been transferred
• The processor is only involved at the beginning
  and end of the transfer

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DMA
The DMA module starts reading each word of the
data and save them in the memory.
procedure readString (var s) Request the DMA
module to read some data now, the
CPU will do something else dont bother
checking I/O status
DMA I/O is more efficient in large data transfer
because the interaction with the I/O module and
data transfer between I/O module and memory are
performed by the DMA module.
After the DMA has transferred all the data
requested to the memory, it notifies that it has
finished the I/O by sending the CPU an interrupt
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Conclusion

• Processor, memory, I/O, bus
• How processor runs program
• How processor interacts with memory and I/O
• Interrupt
• Cache
• Programmed I/O, Interrupt-driven I/O and DMA