System Design for DSP Applications in Transaction Level Modeling Paradigm

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System Design forDSP Applications inTransaction
Level Modeling Paradigm

• Abhijit K. Deb, Axel Jantsch, Johnny Öberg
• Department of Microelectronics and Information
  Technology
• Royal Institute of Technology (KTH), 16440 Kista,
  Sweden
• Email abhijit axel johnny _at_ imit.kth.se

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Outline

• Motivation
• System Design for DSP Applications
• Transaction Level Modeling
• MASIC Methodology
• 3 - Transaction Level Models
• Experiments
• Grammar based language
• Results
• Conclusion

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System design flow In general
functionality
architectural decision
mapping
performance analysis

• studies the functionality
• takes the system specification
• makes few initial calculations
• proposes an architecture
• system performance is evaluated
• architectural decisions are alteredto meet
  performance

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Pros and cons of conventional approaches

• Benefit
• using the best suited models of computation for
  different aspects of the system model
• design reuse through interface based design

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Design flow in MASIC Methodology

• categorize architectural decisions
• system level decisions
• implementation level decisions
• formulate a set of well defined Transaction
  Level Models (TLMs)
• provides
• smooth path to implementation level through
  incremental changes
• avoid expensive top-down iteration

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Transaction Level Modeling

• communication is modeled in a way that is
  accurate in terms of what is being communicated,
  but not in a way that is structurally accurate
• details of communication are separated from the
  details of computation

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System Modeling Graph
A. Functional model B. Process transaction
model C. System transaction model D. Bus
transaction model E. Implementation model
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Outline

• Motivation
• System Design for DSP Applications
• Transaction Level Modeling
• MASIC Methodology
• 3 - Transaction Level Models
• Experiments
• Grammar based language
• Results
• Conclusion

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Functional Model (FM)

• Processes-
• perform blocking read, computation, manipulate
  their own state,non-blocking write
• communicate through infinite FIFOs
• Individual DSP functions are developed in C
• Design issues are primarily algorithmic
• Scheduling-
• the order of process execution has no effect on
  the behavior of the model

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Process Transaction Model (PTM)
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System Transaction Model (STM)

• implementation level decisions
• implementation of the FIFOs
• choice of communication architecture
• add estimated communication delay
• simulate, change decisions if needed

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Bus Transaction Model (BTM)
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Implementation Model (IM)

• For a SW implementation-
• the C functions are compiled to the target
  architecture
• For a HW implementation-
• RTL description of pre-designed HW block
• synthesize in accordance with interface
• Perform cycle accurate simulation of the system

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Outline

• Motivation
• System Design for DSP Applications
• Transaction Level Modeling
• MASIC Methodology
• 3 - Transaction Level Models
• Experiments
• Grammar based language
• Results
• Conclusion

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Grammar Based Language

• Grammar description
• Grammar rules used to describe protocols.
• Constraints to the grammar rules used to specify
  architectural resources like FIFOs,
  synchronization signals, buses, memories, IOs
  (i.e., interface), etc.
• The model captures the concurrent and
  non-terminating behavior of a system

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Example grammar rules
Case - II
Case - I
(data_Rdy, room_Rdy) _at_clk 1, 0
get(in_FIFO, in_Buf) read_Rdy
lt 1 wait until clk 1
read_Rdy lt 0
call c_fun1(in_Buf, out_Buf)
wait for 3 us result_Rdy lt
1 0, 1 put (out_Buf,
out_FIFO) result_Rdy lt 0
... ...
(data_Rdy, room_Rdy) _at_clk 1, 0
null 1, 1 call c_fun2(in_FIFO,
out_FIFO) wait for 5 us
read_Rdy lt 1
wait until clk 1 read_Rdy
lt 0 ... ...
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Case study

• Two examples
• LPC speech codec
• windowing, correlation, LPC, reflection
  coefficient
• SD demodulator
• integrator, differentiator, 31-tap FIR, 69-tap
  FIR filter
• The LPC codec is shown below

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BTM of the LPC example

• 4 DSP functions were mapped to 4 MIPS32-4K cores
• AMBA AHB is used as the communication architecture

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MASIC description of the BTM
- - Protocol of AMBA Slave Controller (HSEL,
HWRITE, HTRANS, HBURST) _at_HCLK '1', '0',
"10", "000" CS lt '1'
RWS lt '0'
HREADY lt '1' '1', '1',
"10", "000" CS lt '1'
RWS lt '1'
HREADY lt '1' '1', '0',
"10", "001" CS lt '1'
RWS lt '0'
HREADY lt '1' branch1
'1', '1', "10", "001" CS lt '1'
RWS lt '1'
HREADY lt '1'
branch2 reset CS
lt '0' RWS
lt '0' HREADY
lt '0' branch1 '-', '-', "11", '-'
CS lt '1'
RWS lt '0'
HREADY lt '1' branch1
'-', '-', "00", '-' branch2 '-',
'-', "11", '-' CS lt '1'
RWS lt '1'
HREADY lt '1'
branch2 '-', '-', "00", '-'
- - grammar rule for the address
decoder (HADDR_HIGH_BIT) "00" HSELv lt
"0001" "01" HSELv lt
"0010" "10" HSELv lt
"0100" "11" HSELv lt
"1000"
- - the memory block of slave_0 (RWS) (CS)
'1' MEM(ADDR) lt HWDATA '0'
HRDATA_0 lt MEM(ADDR) - -
fetching the HADDR at the rising edge of - - the
HCLK of the address cycle (HSEL) _at_HCLK '1'
ADDR lt HADDR
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Results

• Code size and number of states

• VHDL simulation time

• Communication delay figures found from STM and
  BTM
• varied by ?2.98

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Conclusion

• Three TLMs for DSP applications
• smooth path to implementation through incremental
  changes
• easy to create and simulate the TLMs
• avoid expensive top-down iteration
• facilitates reuse of pre-designed blocks
• Language support
• Any DSP system design methodology would benefit
• Exists CAD tool support at the back end
• So far only SDF examples have been considered
• Compilation of the grammar description to SystemC
• Tool support for estimating communication delay
  and automatic synthesis of interfacing logic

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Thank you!

• Questions?