Sequential Circuits

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Sequential Circuits

• Sequential Circuit Definitions
• Latches
• Flip-Flop(FF)
• Sequential Circuit Analysis
• Sequential Circuit Design
• Designing with D Flip-Flop
• Designing with JK Flip-Flops
• HDL Representation for Sequential Circuits

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4-1. Sequential circuit definitions

• Block diagram of a sequential circuit
• state of the sequential circuit
• binary information stored in the storage element
  at any given time
• sequential circuit is specified by
• a time sequence of inputs, internal states, and
  outputs

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Two main types of sequential circuits

• Classification
• the time at which their inputs are observed
• the time at which their internal state changes
• synchronous, asynchronous sequential circuit
• Synchronous sequential circuit
• the knowledge of its signals at discrete instants
  of time
• Asynchronous sequential circuit
• the inputs at any instant of time
• the order in continuous time in which the inputs
  change

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Storage elements

• Using logic circuit (buffer)
• propagation gate delay
• there is no way for the information to be changed
• latches by replacing the inverters with NOR and
  NAND
  asynchronous storage circuits
• design using complex asynchronous circuits
• difficult to design by the propagation delays of
  the gates
• asynchronous latches as block to build
  flip-flops that store information in synchronous
  circuit

Gate output
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Synchronous sequential circuit

• synchronous circuit
• synchronization clock pulse generated by clock
  generator
• clocked sequential circuits clock pulses are
  used as inputs to storage elements
• easy to design in spite of wide differences in
  circuit delays

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Flip-flop

• The storage elements used in clocked sequential
  circuit
• binary storage device with timing characteristics
• flip-flop input combinational circuit and clock
  signal
• flip-flop can change state only in response to a
  clock pulse
• for synchronization, when a clock pulse is
  absent, flop-flop outputs cannot change
• transition occurs only at fixed time intervals of
  the clock pulses
• flip-flop has one or two outputs, one is normal
  and complement

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4-2. Latches

• Storage element
• can maintain a binary state indefinitely until
  directed by an input signal to switch states
• major differences between latches and flip-flop
• the number of inputs to affect the binary state
• flip-flop are usually constructed from latches
• SR Latch using NOR gate

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SR Latch

• Logic simulation of SR Latch behavior
• the propagation delays of the NOR gate 1 ns
• Fig. 4-5
• undesired state when input combination is (1,1)
• in general, the latch state changes only in
  response to input changes and remains unchanged
  otherwise
• SR Latch using NAND gate
• input signal is complement of the SR Latch using
  NOR gates

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SR Latch with control input

• Additional control input
• determine when the state of the latch can be
  changed
• control input C enable signal for the other
  two inputs
• when C0, NAND output1 quiescent condition
• output state does not change
• when C1, SR latch
• all three inputs1 undefined state
• SR latch with control input SR(RS) flip-flop

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D Latch

• Elimination the undesirable undefined state in
  the SR latch
• inputs S and R are never equal to 1 at the same
  time
• two inputs D(data), C(control)
• when C1, D input is sampled and transferred to Q
  output
• hold data D latch

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D latch

• D latch with transmission gates
• when C1, the 2nd TG is disconnected and D is
  connected through two inverters to output Q
• when C0, the 1st TG is disconnected, and loop is
  constructed
• output Q is retained by the loop

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4-3. Flip-Flops

• State of latch in flip-flop
• switch by a momentary change on the control
  input trigger
• latch is transparent
• any changes in the input will change the state of
  the latch while the clock pulse is active
• its input value can be seen from the outputs
  transparent
• the result is an unpredictable situation
• the output of a latch cannot be applied directly
  to the input of the same or another latch
• it is necessary to prevent transparency
  blocking the path from input to output
• two ways to form a flip-flop
• master-slave flip-flop combining two latch
• edge-triggered flip-flop only active during a
  signal transition

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Master-slave flip-flop

• Two latches and an inverter
• when C0, slave latch is enabled and Q Y
• when C1, master latch is enabled and a value
  controlled by SR stored in Y
• SR latch with control input(Fig.4-7) clocked SR
  latch
• logic simulation Fig. 4-11 (1ns gate delay)

master
slave
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JK flip-flop

• modified SR FF eliminate the undesirable
  condition by undefined outputs
• both inputs equal to 1 cause the output to
  complement its value
• pulse-triggered FF change in state during its
  clock pulse

Master-slave JK FF
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Edge-triggered flip-flop

• Ignore the pulse while it is at a constant level
• trigger only during a transition of the clock
  signal
• positive edge(0-to-1 transition, rising edge
  trigger)
• negative edge(1-to-0 transition, falling edge
  trigger)
• D type positive-edge-triggered FF(master-slave
  FF)
• master latch is D latch edge-triggered FF
• during C0, state is changed(transparent) but Q
  is remained
• when the positive edge occurs, state is fixed and
  copied to Q
• during C1, state is unchanged and Q is also
  remained

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Edge-triggered FF

• Consideration of the response timing
• setup time
• minimum time for which the D input must be
  maintained at a constant value prior to the
  occurrence of the clock transition
• hold time
• a minimum time for which the D input must not
  change after the application of the positive
  transition of the pulse
• propagation delay time of the flip-flop
• interval between the trigger edge and the
  stabilization of the output to the new state
• minimum propagation delay time gt maximum hold
  time
• the changes of the outputs are to be separated
  from the control by the inputs

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Positive edge triggered JK FF

• D1 for J1 and Q0 or K0 and Q1
• when J1 with state 0 regardless of K, FF state
  is 1
• when K0 with state 1 regardless of J, FF state
  is 1
• D0 for K1 and Q1 or J0 and Q0
• when K1 with state 1 regardless of J, FF state
  is reset
• when J0 with state 0 regardless of K, FF state
  is remained 0

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Standard graphic symbols

• postponed output indicator output signal changes
  at the end of the pulse
• dynamic indicator response to edge transition of
  the input clock pulse

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Characteristic tables

• Define the logical properties of FF by describing
  its operation in tabular form
• present state Q(t), next state Q(t1)
• clock pulse is occurred between time t and t1

T(toggle) FF tying inputs J and K together from
JK FF
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Direct inputs

• Special inputs for setting and resetting FF
  asynchronously and independently of the clock
  input C
• direct set, preset / direct reset, clear
• JK FF with direct set and reset(IEEE standard
  symbol)