Scaling of High Frequency III-V Transistors

1
Scaling of High Frequency III-V Transistors
Short Course, 2009 Conference on InP and Related
Materials, Newport Beach, CA, May 10-14
Mark Rodwell University of California, Santa
Barbara
rodwell_at_ece.ucsb.edu 805-893-3244, 805-893-5705
fax
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THz Transistors
Transistor bandwidths are increasing rapidly. Si
MOSFETs will soon reach 500 GHz cutoff
frequencies. It is now clear III-V bipolar
transistors can reach 2-3 THz cutoff
frequencies. III-V FETs have comparable
potential, but the prospects and analysis are
less clear. The limits to transistor bandwidth
are contact resistivities gate dielectric
capacitance densities. device and IC power
density thermal resistance. challenges in
reliably fabricating small devices.
3
WhyTHz Transistors ?
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Why Build THz Transistors ?
500 GHz digital logic? fiber optics
THz amplifiers? THz radios? imaging, sensing,
communications
precision analog design at microwave
frequencies? high-performance receivers
Higher-Resolution Microwave ADCs, DACs, DDSs
5
PerformanceFigures of Merit
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Transistor figures of Merit / Cutoff Frequencies
H21short-circuit current gain
MAG maximum available power gainimpedance-matc
hed
fmaxpower-gaincutoff frequency
gains, dB
U unilateral power gainfeedback nulled,
impedance-matched
ftcurrent-gaincutoff frequency
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What Determines Gate Delay ?
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HBT Design For Digital Mixed-Signal Performance
from charge-control analysis
analog ICs have similar bandwidth constraints...
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High-FrequencyElectron Device Design
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Simple Device Physics Resistance
bulk resistance
contact resistance-perpendicular
contact resistance- parallel
Good approximation for contactwidths less than
2 transfer lengths.
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Simple Device Physics Depletion Layers
capacitance
transit time
space-chargelimited current
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Simple Device Physics Thermal Resistance
Exact
Long, Narrow Stripe
Carslaw Jaeger 1959
HBT Emitter, FET Gate
Square ( L by L )
IC on heat sink
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Simple Device Physics Fringing Capacitance
wiring capacitance
FET parasitic capacitances
VLSI power-delay limits
FET scaling constraints
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Electron Plasma Resonance Not a Dominant Limit
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Electron Plasma Resonance Not a Dominant Limit
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Electron Plasma Resonance Not a Dominant Limit
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Electron Plasma Resonance Not a Dominant Limit
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Frequency Limitsand Scaling Laws of (most)
Electron Devices
PIN photodiode
To double bandwidth, reduce thicknesses
21 Improve contacts 41 reduce width 41, keep
constant length increase current density 41
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Bipolar Transistor Scaling Laws
Changes required to double transistor bandwidth
parameter change
collector depletion layer thickness decrease 21
base thickness decrease 1.4141
emitter junction width decrease 41
collector junction width decrease 41
emitter contact resistance decrease 41
current density increase 41
base contact resistivity decrease 41
Linewidths scale as the inverse square of
bandwidth because thermal constraints dominate.
20
FET Scaling Laws
Changes required to double transistor bandwidth
parameter change
gate length decrease 21
gate dielectric capacitance density increase 21
gate dielectric equivalent thickness decrease 21
channel electron density increase 21
source drain contact resistance decrease 41
current density (mA/mm) increase 21
Linewidths scale as the inverse of bandwidth
because fringing capacitance does not scale.
21
THz nm Transistors it's all about the
interfaces
Metal-semiconductor interfaces (Ohmic
contacts) very low resistivity Dielectric-sem
iconductor interfaces (Gate dielectrics)
very high capacitance density Transistor IC
thermal resistivity.
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BipolarTransistors
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Indium Phosphide Heterojunction Bipolar
Transistors
Z. GriffithE. Lind
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Bipolar Transistor Operation
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Transistor Hybrid-Pi equivalent circuit model
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Cutoff frequencies in HBTs
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Epitaxial Layer Structure
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Epitaxy InP Emitter, InGaAs Base, InP Collector,
Both Junctions Graded
M. DahlstromZ. Griffith UCSB M. UrteagaTSC
Key Features N InGaAs emitter contact
layer InP emitter InGaAs/InAlAs superlattice
e/b grade InGaAs graded base bandgap or doping
grade BC setback layer InGaAs/InAlAs
superlattice b/c grade InP collector InGaAs
etch-stop layer thin for heat conduction InP
subcollector
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M. DahlstromZ. GriffithE. Lind
Epitaxy with Abrupt BE Junction
Similar design Abrupt E/B junction (no e/b
grade) Advantagesease of stopping emitter etch
on base? good base contacts DisadvantagesIncre
ased Vbe .Cannot make e/b ledge.
emitter
collector
gradedbase
subcollector
emittercap
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Alternative Grades for Thinner Epitaxy
E . LindZ. Griffith
Common Grade in LiteratureInGaAs/InAlAs 18 nm
thick, 1.5 nm period
Sub-monolayer Grade0.15 nm InAlAs, (0.15 to
0.165 nm InGaAs)10.8 nm thick
Strained InxGa1-xAs Grade InGaAs/GaAs 6 nm
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Other Methods of Grading the Junctions
InGaAs/InGaAsP/InP grade
InP/GaAsSb/InP DHBT
IEDM 2001
- does not need B/C grading - E/B band alignment
through GaAsSb alloy ratio (strain)
or InAlAs emitter
-suitable for MOCVD growth - excellent results
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Transport Analysis
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Approximate Carrier Transit Times
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Base Transit Time with Graded Base
Dino Mensa
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Dino MensaMiguel UrteagaMattias Dahlström
Base Transit Time Grading Approaches
Compositional grading strained graded InGaAs
base
Doping grading unstrained In0.53Ga0.47As base
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T. Ishibashi
Collector Transit Time
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Space-Charge Limited Current Density ? Ccb
charging time
Collector Depletion Layer Collapse
Collector Field Collapse (Kirk Effect)
Collector capacitance charging time scales
linearly with collector thickness if J Jmax
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Space-Charge-Limited Current (Kirk effect) in
DHBTs
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T. Ishibashi
Current-induced Collector Velocity Overshoot
300 Å InGaAs base 2000 Å InP collector 280 GHz
peak ft
J0
J 8 mA/um2
Nakajima, H. "A generalized expression for
collector transit time of HBTstaking account of
electron velocity modulation," Japanese Journal
ofApplied Physics, vo. 36, Feb. 1997, pp.
667-668
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Transit time Modulation Causes Ccb Modulation
Camnitz and Moll, Betser Ritter, D. Root
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Emitter-Base Junction Effects
Electron degeneracy contributes 1 ? -
µm2equivalent series resistance
Space-charge storage
Voltage drops in depletion region
RodwellLundstrom.
need thin layer high electron density
need thin layer to avoid substantial charge
storage delays
42
RC parasitics
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Simple Device Physics Resistance
bulk resistance
contact resistance-perpendicular
contact resistance- parallel
Good approximation for contactwidths less than
2 transfer lengths.
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HBT RC Parasitics
base contact width lt 2 transfer lengths ? simple
analysis
Limiting case of Pulfrey / Vaidyanathanfmax
model.
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HBT RC Parasitics
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Base-Collector Time Constant Fmax.
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Relationship to Equivalent Circuit Model
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Device Design Device Scaling
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Simple Device Physics Thermal Resistance
Exact
Long, Narrow Stripe
Carslaw Jaeger 1959
HBT Emitter, FET Gate
Square ( L by L )
IC on heat sink
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Bipolar Transistor Design
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Bipolar Transistor Design Scaling
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Bipolar Transistor Scaling Laws
Changes required to double transistor bandwidth
parameter change
collector depletion layer thickness decrease 21
base thickness decrease 1.4141
emitter junction width decrease 41
collector junction width decrease 41
emitter contact resistance decrease 41
current density increase 41
base contact resistivity decrease 41
Linewidths scale as the inverse square of
bandwidth because thermal constraints dominate.
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Thermal Resistance Scaling Transistor,
Substrate, Package
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Thermal Resistance Scaling Transistor,
Substrate, Package
Probable best solution Thermal Vias 500 nm
below InP subcollector ...over full active IC
area.
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InP Bipolar Transistor Scaling Roadmap
emitter 512 256 128 64 32 nm width 16 8 4 2 1
???m2 access r base 300 175 120 60 30 nm
contact width, 20 10 5 2.5 1.25 ???m2
contact r collector 150 106 75 53 37.5 nm
thick, 4.5 9 18 36 72 mA/?m2 current
density 4.9 4 3.3 2.75 2-2.5 V,
breakdown ft 370 520 730 1000 1400
GHz fmax 490 850 1300 2000 2800 GHz power
amplifiers 245 430 660 1000 1400 GHz digital
21 divider 150 240 330 480 660 GHz
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Can we make a 1 THz SiGe Bipolar Transistor ?
InP SiGe emitter 64 18 nm width 2 1.2 ???m2
access r base 64 56 nm contact width,
2.5 1.4 ???m2 contact r collector 53 15 nm
thick 36 125 mA/?m2 2.75 ??? V,
breakdown ft 1000 1000 GHz fmax 2000 2000
GHz PAs 1000 1000 GHz digital 480 480 GHz(21
static divider metric)
Simple physics clearly drives scaling
transit times, Ccb/Ic ? thinner
layers, higher current density high power
density ? narrow junctions small junctions?
low resistance contacts Key challenge
Breakdown 15 nm collector ? very low
breakdown (also need better Ohmic
contacts)
Assumes collector junction 31 wider than
emitter. Assumes SiGe contacts 21 wider than
junctions
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HBT Design For Digital Mixed-Signal Performance
from charge-control analysis
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InP HBT Status
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InP DHBTs September 2008
125 nm
250 nm
250 nm
600nm
350 nm
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512 nm InP DHBT
500 nm mesa HBT
150 GHz M/S latches
175 GHz amplifiers
LaboratoryTechnology
UCSB
UCSB / Teledyne / GCS
DDS IC 4500 HBTs
20-40 GHz op-amps
500 nm sidewall HBT
Production
( Teledyne )
Teledyne / BAE
Teledyne / UCSB
Teledyne
Z. GriffithM. UrteagaP. RowellD. PiersonB.
BrarV. Paidi
20 GHz clock
f? 405 GHz fmax 392 GHz Vbr, ceo 4 V
53-56 dBm OIP3 _at_ 2 GHzwith 1 W dissipation
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256 nm GenerationInP DHBT
150 nm thick collector
70 nm thick collector
324 GHzAmplifier
60 nm thick collector
200 GHz master-slavelatch design
Z. Griffith, E. Lind J. Hacker, M. Jones
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324 GHz Medium Power Amplifiers in 256 nm HBT
ICs designed by Jon Hacker / Teledyne Teledyne
256 nm process flow- Hacker et al, 2008 IEEE
MTT-S 2 mW saturated output power
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128 / 64 / 32 nm HBT Technologies
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Conventional ex-situ contacts are a mess
THz transistor bandwidths very low-resistivity
contacts are required
textbook contact
with surface oxide
with metal penetration
Interface barrier ? resistance Further
intermixing during high-current operation ?
degradation
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Improvements in Ohmic Contacts
A.. CrookV. JainA. BaraksharM. WisteyU.
Singisetti S. Bank
128 nm generation requires 4 ? - µm2 emitter
base resistivities 64 nm generation requires
2 ? - µm2
Contacts to N-InGaAsMo MBE in-situ 2.2
(/- 0.5) ? - µm2 TiW ex-situ / NH4
pre-clean 2.2 ? - µm2 variable between
process runs
Contacts to P-InGaAsMo MBE in-situ below
2.5 ? - µm2 Pd/Ti... ex-situ 4 ? -
µm2...far better contacts coming...
measured emitter resistance remains higher than
that of contacts.
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Mo Emitter Contacts Robust Integration into
Process Flow
M. WisteyA. BaraksharU. SingisetttiV. Jain
Proposed Process Integration
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Process Must Change Greatly for 128 / 64 / 32 nm
Nodes
control undercut? thinner emitter
thinner emitter? thinner base metal
thinner base metal? excess base metal resistance
Undercutting of emitter ends
101A planes fast
111A planes slow
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128 nm Emitter Process Dry Etched Metal
Semiconductor
E. Lind
patternmetal
Litho
sidewall
dry etch
wet etch
results _at_ c.a. 200 nm emitter metal width
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Planarization E/B Processes for 64 32 nm
E LobisserV. JainG. Burek
Planarization boundary
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III-V FET Scaling
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Simple FET Scaling
Goal double transistor bandwidth when used in any
circuit ? reduce 21 all capacitances and
all transport delays? keep constant all
resistances, voltages, currents
All lengths, widths, thicknesses reduced 21
S/D contact resistivity reduced 41
If Tox cannot scale with gate length,
Cparasitic / Cgs increases, gm / Wg does not
increasehence Cparasitic /gm does not scale
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FET scaling Output Conductance DIBL
transconductance
output conductance
? Keep Lg / Tox constant as we scale Lg
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FET Scaling Laws
Changes required to double transistor bandwidth
parameter change
gate length decrease 21
gate dielectric capacitance density increase 21
gate dielectric equivalent thickness decrease 21
channel electron density increase 21
source drain contact resistance decrease 41
current density (mA/mm) increase 21
74
III-V MOSFETs for VLSI
What is it ?MOSFET with an InGaAs channel
Why do it ?low electron effective mass? higher
electron velocity more current, less charge at a
given insulator thickness gate lengthvery low
access resistance
What are the problems ?low electron effective
mass? constraints on scaling !must grow high-K
on InGaAs, must grow InGaAs on Si
Our focus today is III-V FET scaling generally
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Low Effective Mass Impairs Vertical Scaling
Shallow electron distribution needed for high
gm / Gds ratio.
Energy of Lth well state
For thin wells, only 1st state can be
populated. For very thin wells, 1st state
approaches L-valley.
Only one vertical state in well. Minimum 5 nm
well thickness. ? constrains gate length scaling.
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Density-Of-States Capacitance
and n is the of band minima
Two implications - With Ns gt1013/cm2,
electrons populate satellite valleys -
Transconductance limited by finite state density
Fischetti et al, IEDM2007
Solomon Laux , IEDM2001
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Drive Current in the Ballistic Degenerate Limits
Error bars on Si data points correct for
(Ef-Ec)gtgt kT approximation
n band minimacdos,o density of states
capacitance for mmo n1
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HEMT Scaling Challenge Low Gate Barrier
Gate barrier is low 0.6 eV
K Shinohara
Tunneling through barrier? sets minimum
thickness
Emission over barrier? limits 2D carrier density
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HEMT Scaling Challenge High Access Resistance
Gate barrier also lies under source / drain
contacts
N layer
widegap barrier layer
K Shinohara
low resistance need low barrier under contacts
low leakage need high barrier under gate
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THz III-V FET Scaling What Must Be Done
As gate length is reduced... channel thickness
should be reduced... barrier thickness should
be reduced... target gm/Wg and Id/Wg should be
increased... source and drain access resistivity
should be reduced... We face serious
difficulties in doing these.
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A MOSFET Might Scale Better than a HEMT
no gate barrier under S/D contacts
high-K gatebarrier
Overlap between gateand N source/drain
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Interconnects
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Coplanar Waveguide
No ground viasNo need (???) to thin substrate
Hard to ground IC to package
ground plane breaks ? loss of ground integrity
III-Vsemi-insulating substrate? substrate mode
coupling Siliconconducting substrate?
substrate conductivity losses
substrate mode coupling or substrate losses
Repairing ground plane with ground straps is
effective only in simple ICsIn more complex CPW
ICs, ground plane rapidly vanishes ? common-lead
inductance ? strong circuit-circuit coupling
poor ground integrity
loss of impedance control
ground bounce
coupling, EMI, oscillation
40 Gb/s differential TWA modulator drivernote
CPW lines, fragmented ground plane
35 GHz master-slave latch in CPWnote fragmented
ground plane
175 GHz tuned amplifier in CPWnote fragmented
ground plane
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Classic Substrate Microstrip
Zero ground inductance in package
Thick Substrate ? low skin loss
No ground planebreaks in IC
High via inductance
TM substrate mode coupling
Strong coupling when substrate approaches ld / 4
thickness
12 pH for 100 mm substrate -- 7.5 W _at_ 100 GHz
lines must be widely spaced
ground vias must be widely spaced
all factors require very thin substrates for gt100
GHz ICs? lapping to 50 mm substrate thickness
typical for 100 GHz
Line spacings must be 3(substrate thickness)
85
III-V MIMIC Interconnects -- Thin-Film Microstrip
narrow line spacing ? IC density
no substrate radiation, no substrate losses
fewer breaks in ground plane than CPW
... but ground breaks at device placements
InP mm-wave PA (Rockwell)
still have problem with package grounding
...need to flip-chip bond
thin dielectrics ? narrow lines ? high
line losses ? low current capability
? no high-Zo lines
86
III-V MIMIC Interconnects -- Inverted Thin-Film
Microstrip
narrow line spacing ? IC density
Some substrate radiation / substrate losses
No breaks in ground plane
... no ground breaks at device placements
InP 150 GHz master-slave latch
still have problem with package grounding
...need to flip-chip bond
thin dielectrics ? narrow lines ? high
line losses ? low current capability
? no high-Zo lines
InP 8 GHz clock rate delta-sigma ADC
87
No clean ground return ? ? interconnects can't
be modeled !
35 GHz static divider interconnects have no
clear local ground return interconnect
inductance is non-local interconnect inductance
has no compact model
8 GHz clock-rate delta-sigma ADC thin-film
microstrip wiring every interconnect can be
modeled as microstrip some interconnects are
terminated in their Zo some interconnects are
not terminated ...but ALL are precisely modeled
InP 8 GHz clock rate delta-sigma ADC
88
VLSI Interconnects with Ground Integrity
Controlled Zo
narrow line spacing ? IC density
no substrate radiation, no substrate losses
negligible breaks in ground plane
negligible ground breaks _at_ device placements
still have problem with package grounding
...need to flip-chip bond
thin dielectrics ? narrow lines ? high
line losses ? low current capability
? no high-Zo lines
89
Conclusions
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Few-THz Transistors
Few-THz InP Bipolar Transistors can it be done ?
Scaling limits contact resistivities, device and
IC thermal resistances.
62 nm (1 THz ft , 1.5 THz fmax ) scaling
generation is feasible.
700 GHz amplifiers, 450 GHz digital logic
Is the 32 nm (1 THz amplifiers) generation
feasible ?
Few-THz InP Field-Effect Transistors can it be
done? challenges are gate barrier, vertical
scaling,source/drain access resistance,
increased gm and drive current. 2DEG carrier
concentrations must increase. S/D regrowth offers
a path to lower access resistance. Solutions
needed for gate barrier maybe even MOSFET ?
91
What Would We Do With Them ?
500 GHz digital logic? fiber optics
THz amplifiers? THz radios? imaging, sensing,
communications
precision analog design at microwave
frequencies? high-performance receivers
Higher-Resolution Microwave ADCs, DACs, DDSs