332:479 Concepts in VLSI Design Lecture 14 Logic Gate Families and Layout

1
332479 Concepts in VLSIDesignLecture 14Logic
Gate Families and Layout

• XOR gates
• Critical Paths
• Logic Layouts
• Transmission Gate Layouts
• Clocked CMOS Logic
• Pass Transistor Logic
• Standard Cells and Gate Arrays
• Summary

• Michael L. Bushnell -- CAIP Center and WINLAB
• ECE Dept., Rutgers U., Piscataway, NJ

2
Material from Principles of CMOS VLSI Design By
Neil E. Weste and Kamran Eshraghian
3
XOR Gates

• nMOS XNOR gate CMOS XOR gate
• Complement A, B, or OUT to get an equivalence gate

B
A
OUT
B
A
B
4
Causes of Incorrect Gate Operation

• Insufficient or noisy power lines
• Gate input noise
• Faulty transistors
• Faulty transistor connections
• Incorrect transistor ratios
• Charge sharing or bad clocking of dynamic gates
• Ratioed and dynamic gates not used in application
  specific integrated circuits (ASICs)
• Used in microprocessors

5
Critical Paths

• Slowest timing paths that limit a chips speed
• Affect critical paths at these levels
• Architecture
• RTL/Logic gate levels
• Circuit level
• Layout level
• RTL/logic level pipelining, gate types, fanin
  fanouts
• Circuit level resize transistors to speed up
• Layout level speed up by changing physical
  layout
• False paths appear to be critical paths, but
  cannot propagate transitions due to Boolean value
  conflicts

6
New Gate Notation

• Bubble on transistor closest to gate output
• Stage ratio increase in transistor size in
  successive logic stages
• Use gates with series inputs of 2-5 for best
  speed

7
Example
8
Worst-Case Rise Delay for m-Input NAND
9
Reformulation
10
New Delay Model

• tdr tinternal-r k toutput-r
• tinternal-r Rp Cg m r
• toutput-r Rp Cg 1 q (k)
• n k
• tf equation is similar
• Assume equal-sized n p transistors

(
)
11
Different Delay Model

• tr tf
• NAND gate Rp m Rn
• Wp Wn
• m
• NOR gate Rn m Rp
• Wn Wp
• m

12
Delay of 1-3 Input Gates
13
Delay of 4-8 Input Gates
14
NAND/NOR Delays Measured with SPICE
15
Effective Channel Resistances
16
Choice of Fastest Gate Implementation
17
Comparison Results for Different 8-Input AND Gates
18
Logic Design Guidelines

• Avoid long resistive charging / discharging paths
  in CMOS
• Use NANDs wherever possible
• Place inverters at high fanout nodes
• Avoid NORs in high-speed circuits
• With fanin gt 4 and large fanout
• Keep fanout below 5-10
• Use minimum-sized gates on high fanout nodes to
  keep CL down
• Keep rising (falling) edges sharp
• When power or area is a constraint, use large
  fanin static gates

19
CMOS Inverter Layouts
20
High Drive Inverters
21
NAND Gate Layout Guidelines

• Use metal3 or highest metal layer for power and
  ground
• Place transistors in complex gates
• Horizontal channels in diffusion
• Vertical poly gates
• Use line of diffusion rule for gate layout

22
NAND Gate Layouts
23
NOR Gate Layouts
24
Complex Logic Gate Layout
25
XNOR Layouts
26
Full-Custom Density Improvement

• Route wires over cells
• Use merged source/drain connections
• Use white space in sparse gates
• Use smaller, optimal device sizes

27
Reducing CL

• Use better physical design

28
Inferior Gate Layout
29
Superior Gate Layout

• Less C on output node

30
Transmission Gate Layouts
31
Two-Input MUX
32
Two-Input MUX
33
Standard (Sandia) Cells

• Fixed height (pitch)
• Width varies with gate function
• Automatically placed in rows and wires routed by
  Cadence Envisia tool

34
Example Standard Cell
35
More Standard Cell Layouts
36
More Standard Cell Layouts
37
Gate Array (Sea of Gates) Layout
38
Sea of Gates Layout
39
Gate Array Layouts

• Isolate gates from each other with vertical poly
  strips tied to VSS (VDD)

40
Clocked CMOS Dynamic Logic

• C2MOS Used to
• Interface with dynamic CMOS logic
• Same input C as static CMOS longer tr tf
• Faster if clocking transistors at center
• Better for hot e-- problems if clock transistor
  is next to ground
• CLOCK is last input to change
• However, this defeats the isolation purpose of
  C2MOS

41
Clocked CMOS Logic
CLK
CLK
42
Summary

• XOR gates
• Critical Paths
• Logic Layouts
• Transmission Gate Layouts
• Clocked CMOS Logic
• Pass Transistor Logic
• Standard Cells and Gate Arrays