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16 BIT KOGGESTONE TREE ADDER

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Seek advice from Dr. Parent and previous students. Save time for debugging error. 16 ... Thanks to Dr. David Parent. Thanks to all 166, 167, and 224 students ... – PowerPoint PPT presentation

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Title: 16 BIT KOGGESTONE TREE ADDER


1
16 BIT KOGGE-STONE TREE ADDER
  • Shayan Kazemkhani
  • Nghia Do
  • Jia Kang Yu
  • Toan Luong

Advisor David Parent May 8th 2006
2
Agenda
  • Abstract
  • Introduction
  • Why Tree Adder?
  • Theory
  • Project Details
  • Summary of Results
  • Lessons Learned
  • Cost Analysis
  • Conclusion

3
Abstract
  • We designed 16 bit Kogge-Stone Tree Adder - the
    most commonly used parallel prefix
    carry-lookahead adder topology.
  • 200MHz clock frequency
  • Area 1000600 um2
  • Power density
  • AMI06 Technology

4
Introduction
  • Why? - minimum logic depth, wide wiring channels,
    regular structure and large fanout points.
  • Prefix Adder Structure

5
  • PROJECT DETAILS
  • 17 pin outs
  • 33 input D-flip flops and 17 output D-flip flops
  • Create schematic and layout for 16 bit tree adder
  • Test schematic using test bench
  • Run DRC and LVS to verify the design

6
BLOCK DIAGRAM
7
Longest path calculation
Tphl 5ns/(143) .29ns
8
Table of actual Wn Wp
9
Schematic
10
Layout
11
DRC Report
12
Extraction report
13
LVS Report
14
Cost Analysis
  • Estimate amount of time spent on project
  • - Verifying NC Verilog 5 hrs
  • - Verifying Timing 10 hrs
  • - Layout 40 hrs
  • - Post Extracted Timing 10 hrs

15
Lessons Learned
  • Start early
  • Work in group
  • Study previous projects
  • Seek advice from Dr. Parent and previous students
  • Save time for debugging error

16
Conclusions
  • We designed and implemented a 16 bit Kogge-Stone
    Tree Adder that operates at 200MHz in an area of
    1000600 um2

17
Acknowledgements
  • Thanks to Cadence Design Systems for the VLSI lab
  • Thanks to Dr. David Parent
  • Thanks to all 166, 167, and 224 students
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