Challenges in Sleep Transistor Design and Implementation in LowPower Designs

1
Challenges in Sleep Transistor Design and
Implementation in Low-Power Designs

• Dr. Kaijian Shi,
• Synopsys Inc. (Professional Services)
• David Howard,
• Arm Ltd.

2
Content

• Power gating and sleep transistors
• Coarse-grain sleep transistor implementations
• Sleep transistor design challenges
• Switch (Ion/Ioff) efficiency
• IR-drop considerations
• Sleep transistor implementation challenges
• Wakeup latency
• Power-on current rush
• Summary

3
Power gating and sleep transistors
L-VTH logic cells

• Leakage trend

4
Ring style sleep transistor implementation
Global VDD
VDD

• Sleep transistors are placed around each VVDD
  island
• No VDD straps in VVDD areas unless state
  retention cells are used

5
Grid style sleep transistor implementation
Global VDD
VDD
VVDD2
VVDD1
VVDD2
VVDD1
VVDD2
VVDD1

• VDD network cross chip VVDD networks in each
  gating domain
• Sleep transistors are placed in grid connecting
  VDD and VVDDs

6
Sleep transistor design challenges

• Sleep transistor introduced penalties
• Aera of the sleep transistors
• IR-drop on sleep transistors
• Power in sleep transistors

• Penalties must be smaller than leakage saving
• Sleep transistor optimization (L, W, Vbb,
  fingers)
• Switch efficiency (Ion/Ioff ratio)
• Area efficiency (Ion/area)
• IR-drop considerations

7
Switch efficiency normal vs reverse back-bias

• Saddle curve
• Max Ion/Ioff at L130nm
• Drop quickly until W1.6um

8
IR-drop consideration Ron with L, W, Vbb

• Ron (Vds/Ids) equivalent channel resistance at
  Vds10mV
• Ron is linearly increased with L and Vbb
• At a same leakage, Ron is significantly smaller
  by Vbb than by L

9
Wakeup latency and current rush

• Wakeup latency mainly the time to charge a
  design to a full power-on state
• Performance hit
• Large charging current at wake up
• Simultaneous charging power nets
• Crowbar current
• ? Large IR-drop ? malfunction, data corruptions
• A practical solution
• Two stage power-on charge method

10
Two daisy-chains weak and main

• Weak sleep transistor chain -gt trickle charge to
  close to Vdd
• Main sleep transistor chain -gt fully charge and
  main operation

11
Trickle charge end control Delay line vs.
Schmitt trigger
Main chain
Main chain
Trickle chain
Trickle chain
VVdd

• Controllability
• Implementation complexity

Sleep
12
Summary

• Optimal sleep transistor design and
  implementation are challenge which requires
  overall considerations of
• Switch efficiency (Ion/Ioff ratio)
• Area efficiency (Ion/area)
• IR-drop considerations
• Power-on current control is critical to a power
  gating design to avoid large IR-drop and VDD
  collapse
• Sleep transistor introduced area, power and
  performance penalties must be smaller than
  leakage saving benefit to be production worthy.

13
Thank you!
14
Coarse grain sleep transistor implementation

• Array of sleep transistors connect between
  permanent Vdd and virtual Vdd nets
• Global VVdd supply all logic cells

15
Trickle charge voltage with weak T size

• Header switches are on 6 row by 4 column grids
• 45 cells in each grid consider Cload, Cvdd, Rvdd

16
Trickle charge current with weak T size