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Tutorial: Leakage Power Modeling and Control Strategies

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Title: Tutorial: Leakage Power Modeling and Control Strategies


1
Tutorial Leakage Power Modeling and Control
Strategies
Joan Figueras, UPC, Spain Enrico Macii,
Politecnico di Torino, Italy CLEAN
WORKSHOP Lisbon, Portugal September 8, 2008
2
AGENDA
  • Module 1
  • Introduction.
  • Modeling Leakage currents.
  • Control techniques at device level
  • Module 2
  • Leakage control strategies
  • Control at circuit/logic level
  • Architectural and Memory Techniques

3
Outline Module 1
  • Introduction
  • Leakage currents
  • Low Power design capabilities. ITRS Roadmap
  • Leakage control at device level

4
Challenges
  • Power consumption of nanoelectronics is a
    limiting factor for commercial exploitation on
    any mobile terminals
  • Leakage Power may soon become the dominating part
    of total power consumption
  • Nanometric processes have large process
    variations, in particular in their leakage
    currents. This leads to severely impact the
    products yield.
  • EDA support for low leakage today is extremelly
    poor and primitive.

5
VDD (no more) scaling is increasing the  power
crisis  ?
5V plateau
Regular Decrease in 10 years From 5V to 1.2V (x
0.7 per node)
1V plateau ???
1.2V plateau
1.1V
120
90
65
32
250
350
700
45
500
180
6
Power Trend for microprocessors
  • Power density in Intels microprocessors

7
Dynamic vs. Leakage Power
Source ITRS Roadmap 2007
Power Consumption
Physical Gate Length nm
8
International Technology Roadmap for
Semiconductors ITRS http//www.itrs.net/
  • For high-performance applications, Effective
    Oxide Thickness of less than 1 nm with adequate
    reliability is needed.
  • Introduction of higher dielectric constant
    (high-?) material in which tunneling current can
    be suppressed without sacrificing current drive
  • Planar MOSFET requires high-channel doping to
    control short-channel effects,
  • the trade-offs are mobility degradation and
  • increased leakage power consumption.
  • Using doping to control threshold voltage in
    scaled device also causes increasing variation of
    the threshold voltage,
  • New device architecture such as ultra-thin body,
    Fully Depleted-SOI, Strained Si, Multiple-gate
    MOSFETs (e.g., finFETs)

9
Silicon structures
Source STMicroelectronics
10
Interconnect solutions
Source STMicroelectronics
11
International Technology Roadmap for
Semiconductors ITRS http//www.itrs.net/
  • Circuit techniques to contain system active and
    leakage power
  • include multiple VDD domains,
  • clock distribution optimization,
  • frequency stepping,
  • interconnect architectures,
  • multiple VTH devices,
  • well biasing,
  • block shutdowns.
  • The implementation challenges require
    improvements in
  • CAD design tools for power optimization
  • Design robustness against process variability
  • leakage and performance requirements of new
    device architectures.

12
Design Flow Adding the Power Dimension
13
Leakage Power
14
Increasing Contribution of Leakage Power
15
Leakage Currents in Bulk CMOS
  • Isub Subthreshold current.
  • Igs, Igb, Igd Gate oxide tunneling.
  • IBTBTs, IBTBTd Junction reverse current.
  • IGIDL, IGISL Gate induced D,S leakage.

GATE
DRAIN
SOURCE
IG
Igb
Igd
Igs
ID
IS
Isub
IGIDL
IBTBTs
IGISL
IBTBTd
IB
BULK
SHORT CHANNEL L 90nm, Tox
2nm Subthreshold Gate leakage
PRESENT and FUTURE L lt 65 nm Subthreshold
Gate BTBT
OLD TECHNOLOGIES Long channel L gt
180nm DOMINATE Subthreshold leakage
16
Leakage Currents in a CMOS INVERTER
Subthreshold Leakage BTBT Leakage Gate Leakage
OFF Gate Leakage ON
OFF
ON
Low Power Technology with Triple well option C.
Pacha INFINEON
17
Subthreshold Leakage Current
G
VGS
D
S
VDS
G
N
N
IDS,Subth
B
B
18
Subthreshold LOGIC Optimal VDD
19
ILEAK-Subthreshold dependence on VTH
log IDS
  • High VTH transistors (slow and non leaky) on
    gates outside the critical path(s)

I0
IL
S
  • Low VTH transistors (fast and leaky) on gates in
    the critical path(s)

IL
0
VGS
Low VTH
High VTH
20
Short Channel Effects
21
Short Channel Effects
22
Gate-induced Drain Leakage
VDS VDD
VGS
log IDS
N
P
IGIDL
Drain
n-poly gate
IDS,Subth
Tunneling Electron
VGS
0
23
Subthreshold Leakage
? Drain Induced Barrier Lowering (DIBL)
24
Subthreshold Leakage
Subthreshold Leakage current statistical
variability
25
Gate Direct Tunneling currents
26
Direct Tunneling Gate Leakage
27
Band to Band Tunneling Leakage
p region
n region
EC EV
qVapp
VDD
EC EV
IBTBT
IBTBT
28
PMOS Tox and Leff Statistical Monte Carlo
Independent Gaussian Distributions 3s Tox4
and 3s Leff4
X 10 -6
BPTM 65nm Nominal Tox1.7nm Nominal Leff33nm
BPTM 45nm Nominal Tox1.4nm Nominal Leff24nm
I Subthreshold
IGATE
X 10 -8
29
NMOS Tox and Leff Statistical Monte Carlo
Independent Gaussian Distributions 3s Tox4
and 3s Leff4
X 10 -7
BPTM 65nm Nominal Tox1.7nm Nominal Leff33nm
BPTM 45nm Nominal Tox1.4nm Nominal Leff24nm
I Subthreshold
IGATE
X 10 -7
30
Scaling Trends Process Variability Monte Carlo
NMOS BPTM 65nm
31
Scaling Trends Process Variability Monte Carlo
NMOS BPTM 45nm
32
CMOS Leakage Power with Subtrheshold, Gate, and
Bulk leakage
Dynamic Power Pdynamic-C PSC PLEAK-active
Quiescent Power PLEAK-inactive
IBulk
IBulk
33
Leakage Power Trends
Inactive circuit Tslack or no clock
Active Circuit (switching)
  • Leakage Power (mainly caused by subthreshold
    currents)

Dynamic Power caused by Capacitive switching
Short Circuit currents
PAST
  • Inactive LEAKEAGE POWER
  • Isubthreshold
  • GATEtunneling
  • I BTBT
  • Dynamic Power caused by Capacitive switching
    Short Circuit currents
  • Active LEAKAGE POWER

PRESENT AD FUTURE
34
Comments
  • Scaling Trends 65?45nm
  • Nominal
  • ISubthreshold 14nA to 35nA ? 2.5X
  • IGate 11nA to 60nA ? 5.45X
  • Variability 3s
  • ISubthreshold 7.5nA to 32.5nA ? 4.3X
  • IGate 17.5nA to 80nA ? 4.6X
  • Correlation ISubthreshold vs. IGate
  • 65nm 0.32 ? 0.41
  • 45nm 0.20 ? 0.22 Correlation decreases with
    scaling
  • Significant Increase of nominal leakage and
    variability due to scaling

35
Thermal dependence
36
Thermal Dependence ION Current
Dependence of drain current with temperature due
to the mobility and threshold voltage
dependences mobility reduction is the main factor
37
Thermal Dependence GIDL Current
Weak dependence of GIDL current due to physical
mechanism of tunneling current
38
Thermal Dependence Gate Current
Very weak dependence of gate current due to
physical mechanism of tunneling current
39
Thermal Dependence IOFF (Subthreshold) Current
Strong dependence of IOFF current due to the high
dependence of subthreshold slope on
temperature -gt Ion/Ioff decreases with temperature
40
Thermal Dependence Summary
41
Thermal Dependence Electro-Thermal Coupling
42
Thermal map of a Multi Processor SoC
Chip floorplan
Steady state temperature
  • Some hot spots in steady state
  • Silicon is a good thermal conductor (only 4x
    worse than Cu)
  • and temperature gradients are likely to occur on
    large dies
  • Lower power density than on a high performance
    CPU
  • (lower frequency and less complex HW)

43
Speed vs. Leakage
44
Multi VTH Delay vs.Voltage VDD and VTH dependency
  • Fast transistors lt low VTH gt LEAKY
  • Slow transitors lt high VTH gt non Leaky
  • VDD is the supply voltage
  • VTH is the threshold voltage
  • is a technology-defined constant between 1
    and 2
  • is 1.2-1.6 for present generation

Delay
VTH gtVTH
VTH
Delay at Nominal VDD, VTH
VDD
VDD
VTH
VTH
45
90/65/45 nm Speed vs Leakage
Source STMicroelectronics
46
LEAKAGE POWER
PLEAK ILEAK VDD
  • IC Manufacturing SCALING trends
  • Ldrawn VDD VTH
    ILEAK-subtrh
  • Tox IGATE
  • DOPPING IBTBT
  • Process Variations

47
Device Level Leakage Control
48
Controlling Subthreshold leakage
log IDS
I0
Increase VTH Reduce SCE (control VTH ) Increase
the INVERSE SLOPE S mV/decade SOI and
MuGFET Lower the Temperature
IL
S
S
0
VGS
Low VTH
49
Controlling Gate leakage
SOLUTIONS High K dielectrics
Multi-Tox transistors
T. Shulz Infineon Tecnologies
50
Controlling BTBT leakage
Schematic view of localized halo and retrograde
well profiles.
PMOS and NMOS BTBT currents for complementary
doping profiles. L25nm MUK,05
51
Process Induced Strain speed enhancement
Source STMicroelectronics
52
Current Research on MOS devices
Gate stack
Bulk
Channel electrostatic control
3D
planar
MuGFET MuCFET …
PDSOI
FDSOI
µ ?
high µ materials
strain
07
09
12
15
65nm
45nm
32nm
22nm
53
Leakage aware design strategies
HS Power Management DVS, DFS, DVFS Adaptive
Leakage Control ABB, AVFS, ASB Adaptive
RECONFIGURATION Cache Memory strategies
RECONFIGURABLE CIRCUITS Voltage/freq
ISLANDS Sleep Transistors BIASING
Body, Source CIRCUITS with Multi VDD
speed VTH Tox
Real Time OS Compile time techniques Algorithms
for leakage control Cache Memory strategies

Emerging DEVICES High K , Multi-Gate
FETs Lithography, Doping, Tox …
54
Leakage Crisis Is it a Technology Issue Only?
  • Trends
  • Nominal Vdd is getting stable around 1V.
  • MOSs VTH linearly scales to keep constant
    speed.
  • But … Leakage grows exponentially with VTH
    reduction !!
  • Gate currents (SiO2) may become larger than
    subthreshold currents.
  • Leakage power can only be limited by combining
    technology and design solutions.

55
Conclusions
  • The electronics market calls for low-power
    circuits and systems.
  • Semiconductor market is still heavily CMOS
    dominated
  • Switching and leakage power.
  • Leakage will become dominant for technology nodes
    below 65nm.
  • Leakage power optimization mudt be addressed from
    both technology and design points of view.
  • Many circuit-level techniques have been
    investigated recently
  • Not yet fully supported by commercial EDA tools.
  • Higher-level approaches are still in their
    infancy
  • Results are promising.
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