Efficient Error Detection, Localization, and Correction for FPGABased Debugging

1
Efficient Error Detection, Localization, and
Correction for FPGA-Based Debugging

• John Lach1William H. Mangione-Smith1Miodrag
  Potkonjak2UCLA Departments of Electrical
  Engineering1and Computer Science2

This work was supported by the Air Force Research
Laboratory of the United States of America, under
contract F30602-96-C-0350 and subcontract QS5200
from Sanders, a Lockheed Martin company.
2
Outline

• Background
• debugging
• emulation
• Motivation
• Related work
• Tiling
• Design changes
• Experimental results
• Conclusions

3
4-Step Iterative Debugging
Test Pattern Generation
4
4-Step Iterative Debugging
Test Pattern Generation
Error Detection
5
4-Step Iterative Debugging
Test Pattern Generation
Error Detection
Error Localization
6
4-Step Iterative Debugging
Test Pattern Generation
Error Detection
Error Localization
Error Correction
7
4-Step Iterative Debugging
Test Pattern Generation
Error Detection
Error Localization
Error Correction
8
Emulation

• Designs mapped to FPGAs for functional test and
  debug
• Hardware provides faster simulation environment
  than simulation
• enables more complex testing and higher
  pre-tapeout confidence
• Design error corrections made at some level of
  design abstraction (HDL, RTL, netlist, etc.)
• Altered design re-placed and re-routed for next
  debugging iteration
• Used for debugging of UltraSPARC-IGateley, et
  al., DAC 95

9
Motivation

• Emulation-based debugging requires multiple
  physical design iterations
• error detection and localization requires
  insertion of control and observation logic in
  physical design
• error correction requires functional physical
  design alterations
• Design must be re-placed and re-routed for each
  iteration
• Excessive time and back-end CAD tool effort
  between each debugging iteration

10
Related Work

• Minimize logic re-synthesis for multiple
  iterations at higher level of abstractionBrand,
  et al., ICCAD 94Swamy, et al., ISCS 97
• Minimize lower level design perturbation
  resulting from higher level changes Kirovski and
  Potkonjak,DAC 99
• Incremental place-and-route
• Quick_ECO Fang, Wu, and Yen, DAC 97
• localizes physical design changes to functional
  blocks
• back-end CAD tool need only re-place and re-route
  affected blocks

11
Goal
Further reduce time between debugging iterations
by decreasing back-end CAD tool effort through
finer-grained physical design partitioning
12
Tiling

• FPGA physical design layout partitioned into
  independent blocks
• spare resources for logic introduction and
  place-and-route flexibility
• Interface between tiles is fixed
• Physical design alterations are localized to
  tiles
• logic introduction for error detection and
  localization
• error correction
• Back-end CAD tool need only re-place and re-route
  affected tiles

13
Tiling ExampleEngineering Implementation Change

• Four functionally equivalent tiles
• Implementation changes are localized to affected
  tiles
• Locked interface to neighboring tiles reduces
  necessary re-place and re-route effort

14
Tiling ExampleEngineering Functional Change

• Two different functions in same tile space
• Functional design changes are localized to
  affected tiles
• Locked interface to neighboring tiles reduces
  necessary re-place and re-route effort

15
Emulation Flow
PR with Slack
16
Emulation Flow
PR with Slack
Tile Design
17
Emulation Flow
PR with Slack
Tile Design
Determine Test Points
18
Emulation Flow
PR with Slack
Tile Design
Determine Test Points
Generate Test Patterns
19
Emulation Flow
PR with Slack
Tile Design
Determine Test Points
Generate Test Patterns
Introduce Control Logic
20
Emulation Flow
PR with Slack
Tile Design
Determine Test Points
Generate Test Patterns
Introduce Control Logic
Introduce Observation Logic
21
Emulation Flow
PR with Slack
Tile Design
Determine Test Points
Generate Test Patterns
Introduce Control Logic
Synthesize Map Design
Introduce Observation Logic
22
Emulation Flow
PR with Slack
Tile Design
Determine Test Points
Generate Test Patterns
Introduce Control Logic
Synthesize Map Design
PR Affected Tiles
Introduce Observation Logic
23
Emulation Flow
PR with Slack
Tile Design
Determine Test Points
Generate Test Patterns
Introduce Control Logic
Identify Affected Tiles
Synthesize Map Design
PR Affected Tiles
Introduce Observation Logic
24
Emulation Flow
PR with Slack
Tile Design
Determine Test Points
Generate Test Patterns
Correct Errors
Introduce Control Logic
Identify Affected Tiles
Synthesize Map Design
PR Affected Tiles
Introduce Observation Logic
25
Emulation Flow
PR with Slack
Tile Design
Determine Test Points
Generate Test Patterns
Correct Errors
Emulation Loop
Introduce Control Logic
Identify Affected Tiles
Synthesize Map Design
PR Affected Tiles
Introduce Observation Logic
26
Tiling Issues

• Tile boundaries
• minimize inter-tile interconnect
• Tile size (granularity)
• size and number of control and observation points
• size of engineering changes expected
• back-end CAD tool effort decreases with smaller
  tiles
• area and timing overhead increases with smaller
  tiles
• Tile shape
• macros
• shape of control and observation logic

27
Linking Design Changes

• Control and observation logic introduction
  anderror correction
• Existing CAD techniques utilize back annotation
  to establish dependence
• tree structure dependence
• Tiling exploits one-to-one linkage between
  abstraction levels in design hierarchy down to
  physical level
• Quick_ECO links down to netlist
• Current work involves providing high level CAD
  tools with more specific target device information

28
Updating Design Changes

• Affected tiles cleared
• interfaces are maintained
• affected interfaces require clearing of
  neighboring tiles
• Unaffected tiles and interfaces locked in
  location
• errors cannot be introduced into rest of design
• Remaining logic re-placed and re-routed in
  cleared tiles
• Interfaces re-locked
• Next functional test iteration begins

29
Experimental Results - Area

• 20 area overhead for logic introduction and
  place-and-route flexibility
• Design sizes reflect range of functional block
  sizes
• Xilinx 4000 CLBs

Design Area
30
Experimental Results - Timing

• Post-tiling timing impact
• Iterative timing overhead depends on design
  changes
• Functional test not concerned with performance
• Design eventuallyre-placed andre-routed for
  tapeout

Timing Overhead
31
Place-and Route Speedup
32
Logic Introduction - Size
100
9sym
styr
90
sand
c499
planet1
c880
80
s9234
MIPS R2000
DES
affected tiles
1
10
19
28
37
46
55
64
73
82
91
100
size of new logic ( CLBs)
33
Logic Introduction - Points
34
Conclusion

• Emulation useful for design debugging
• more complex simulations than in software
• Tiling provides finer-grained physical design
  partitioning
• Links design changes to physical design level
• Reduces re-place and re-route effort
• Decreases time between debugging iterations
• allows added simulation time for increased
  pre-tapeout confidence
• decreases time-to-market of design