Interrupt

1
Interrupt

• Asynchronous events that redirect the program
  flow
• Hardware activity
• Save the context of the processor
• Execute interrupt acknowledge cycle
• Branch to a predetermined address
• Restore the context of the processor
• Return to the interrupted code
• Software activity
• Initialize hardware vector table, parameters,
  enabling
• Interrupt Service Routine

2
Interrupt Vectors

• A method to discriminate interrupt sources
• Methods
• Interrupt number used for address calculation
• Actual instruction used for branch
• Implementations
• Fig. 4.1
• Interrupt priority
• Assign different priority to interrupt sources
• 68000 vs. Intel 8259

3
Interrupt hardware (1)

• External interrupt
• A pin per interrupt source on a processor
• Each pin has a vector address
• Only one pin on a processor
• Require interrupt acknowledge cycles
• 8086 INTA, 68000 status bits
• Internal interrupt
• Each source has a vector address
• Multiple source share a vector address

4
Interrupt hardware (2)

• Daisy-chained interrupt
• Fig 4.2
• Fewer interrupt lines are needed.
• But, priority is fixed.
• NMI
• Cannot masked
• Power-fail, invalid-instruction, divided-by-0

5
Level-sensitive interrupt

• Interrupt is indicated when and only when the
  signal pin is in an active state.
• Pros
• Signal line can be shared.
• Cons
• ISR must clear the interrupt request.
• Avoid getting stuck -gt always active interrupt

6
Edge-sensitive interrupt

• Interrupt is indicated on a rising or falling
  edge of the signal pin.
• Pros
• Ideal for counting events
• Cons
• Avoid getting stuck -gt always inactive interrupt
• Hard to share interrupt lines
• Polling the device status
• Arbitration
• Would miss interrupt request
• Use timer-counter scheme

7
Interrupt Service Routine(ISR)

• Service interrupt
• Processing the required work
• Clear the interrupt request if necessary
• Enable the system for further interrupt
• Implicit return instruction
• Explicit separate instructions
• Return control
• Interrupt lets the all registers to be saved

8

• Nested interrupt
• ISR maybe interrupted by other interrupts.
• Stack size
• Passing data to or from the ISR
• Cannot use registers or stack
• Use flags(global variables)
• Checking the stuck interrupt
• Cycle time of polling loop lt interrupt interval
• Check a flag set by polling loop
• Cycle time of polling loop gt interrupt interval
• Check a counter set by ISR

9
Data corruption (1)

• Shared memory or I/O register
• Interrupt should be disabled in critical
  sections.
• Ex)
• Main code
• Read location 0x1000
• OR the value 01 with the data from 0x1000
• Store the result back at 0x1000
• Interrupt service routine
• OR the value 0x20 into location 0x1000

10
Data corruption (2)

• Race condition
• Write-after-write hazard
• Ex)
• If input data are available
• Set FLAGBYTE
• ---- interrupted ----
• Store input data at DATABYTE

11
Data corruption (3)

• Cumulative time errors
• The delay between assertion of the interrupt and
  execution of the ISR
• Use hardware timer having auto-restart

12
Data corruption (4)

• Multiple reads
• The value of a location that would be accessed by
  ISR
• Ex)
• Read location 0x1000
• If 0x1000 0, do something
• Read location 0x1000 again
• If 0x1000 1, do something different
• .

13

• Minimizing interrupt service time
• Ex)
• ISR code 1
• Read from input
• Check for error
• Move the data to buffer
• Return
• ISR code 2 ( polling loop)
• Set flag
• Return

14
When to use interrupt

• Interrupts make the debugging hard.
• In some cases, interrupt cannot be a solution for
  timing problems
• Ex) low-priority ISR incurs delayed execution.