CS 891S M.tech ProjectI

1
CS 891S M.tech Project-I

• FSM Derivation from SystemC Models
• Under the guidance of
• Assistant Prof. Preeti Ranjan Panda,
• Computer Science Department,IIT Delhi.
• Presented by
• Risheedhar S
• (Entry No. 1997405)

2
Layout of the Presentation

• Introduction
• Objective
• Problem Statement
• Study done regarding
• 1.SystemC
• 2.Sage
• Basic Idea and thought process.
• Work done till now.
• Future work

3
Introduction

• As more and more complex Embedded systems must be
  built, design process should be shifted towards
  higher levels of abstraction.
• A specification method for design and validation
  of Embedded systems must have both a suited
  execution semantic and a definition of time and
  concurrency.

4
Motivation

• After hardware allocation and scheduling,
  control  and dataflow information represented in
  the form of FSM, allows design changes without
  spending huge amounts of time reimplementing the
  whole control logic again.

5
Problem Statement

• Given a SystemC Description with arbitrarily
  complex loops, derive a FSM which describes the
  control flow implemented depending on the wait()
  statements.

6
Study done regarding SystemC

• C class library provides a cycle-based
  simulation kernel and necessary constructs needed
  to create a cycle accurate system model.
• C dialect to model digital systems.
• Why SystemC?
• Libraries are freely distributed.
• C Language definition is publicly available.
• SystemC has a notion of real time.
• Model verification is possible.

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Study done regarding SystemC.contd

• Easy to write deterministic programs in SystemC.
• Dont share variables among processes
• Communicate through signals
• Dont try to store state in SC_METHODs
• Possible to introduce nondeterminism
• Share variables among SC_CTHREADs
• They are executed in nondeterministic order
• No control over how many times the SC_METHODs
  are invoked.

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Study done regarding Sage

• Its an object oriented, open, C class library
  that provides the user with a set of parsers, a
  structured parse tree, a symbol and type table
  .a compiler toolkit.
• It gives the user freedom to parse any
  FORTRAN/C program, restructure the internal
  form(.dep file), and further unparse to generate
  new source code out of the restructured internal
  form.

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Sage Library Class Hierarchy
Sage base class
Projects and files
Statements
Expressions
Symbols
Types
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Study done regarding Sagecontd

• Limitations of Sage
• Its not easy for the user to add language
  extensions to Fortran/C to the system.
• ( a new node type must be added to the internal
  form and corresponding subclass added to Sage
  hierarchy and unparser module should be able to
  recognise this new node)
• There is mismatch in types that Sage reads and
  the standard GNU ones.

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FSM Derivation for SystemC Models
Extract statements, expressions, symbols,wait() s
Given a SystemC description
Figure out the loop statements and derive the
FSM
Using compiler toolkit i.e, Sage here
Using some optimising techniques
Display the FSM in a suitable Format (mealy
machine format) (FSM viewer)
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Basic idea

• Extract the control statements i.e if-then-else,
  for, do-while and case statements.
• find the loop variables and their scope.
• Extract the wait() ,wait_until(),next_trigger()
  statements and other dataflow expressions in
  between.
• The wait() statements act as state boundaries.

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F() wait() vari
while(varltlimit) A() . wait()
B() var C()
wait() D() wait()
Mealy machine
1
1
varivarltlimit / A()
2
2
B()varvargtlimit / C()
3
3
--/ D()
B()var varltlimit / A()
4
4
14
--/A()
f() A() wait() B()
if(X) C() . wait()
D() else
E() wait()
F() G()
wait() h()
Mealy machine
1
1
B()X / E()
B() X / C()
2
3
2
3
--/D()G()
--/ F()G()
4
4
--/h()
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f() wait() for(varivarltlimitvar)
A() . wait()
B() C() wait() h()
1
Mealy machine
1
2
varivarltlimit / A()
2
B()vargtlimit / C()
3
3
B()varvarltlimit /A()
--/h()
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f() wait() case(i) i1
A()wait()break i2 B()wait()break i3
C()wait()break defaultD()wait()break E()
wait() h()
1
Mealy machine
1
default/ D()
2
3
i3 / C()
i1/A()
4
5
i2 /B()
4
5
2
3
--/E()
--/E()
--/E()
--/E()
6
6
--/h()
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Work done till now

• Learnt SystemC,Sage compiler toolkit.
• I am able to extract the loop statements,expressio
  ns and symbols and their scope specification from
  a given C program using Sage.
• Trying to figure out wait() statements by the
  variant of the statement as Sage recognizes.

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FSM Derivation for SystemC Models
Extract statements, expressions, symbols,wait() s
Given a SystemC description
Figure out the loop statements and derive the
FSM
Using compiler toolkit i.e, Sage here
Display the FSM in a suitable Format (mealy
machine format) (FSM viewer)
Using some optimising techniques
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Future Work

• Need to update the inconsistencies between Sage
  and the standards.
• Completely derive FSM from a known SystemC
  description.
• Work on descriptions with more complex loops and
  find the consistency of the FSM generated.
• Make a display to output the FSM generated in a
  suitable format.

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• Thank you