Using Data path merging as high level synthesis method for Run Time Reconfigurable systems

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Using Data path merging as high level synthesis
method for Run Time Reconfigurable systems
Mahmood Fazlali Shahid Beheshti University
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Outlines
High Level Synthesis
Data path Merging
Configuration Time Reduction By Data path Merging
Future Works (Possible Researches)
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High Level Synthesis
Data path Merging
Configuration Time Reduction By Data path Merging
Future Works (Possible Researches)
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Hw/swpartitioning
System Specification C/C Variants
HW/SW Partitioning
Data Dependent parts
Control Dependent Parts
Software Compiler
High Level Synthesis Tool
Assembly/Machine Code Generation
Logic Synthesis And PR

Processor Core
Reconfigurable Unit
Memory Unit
I/O
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Computer Aided Design
Data Dependent parts
Compilation
CDFG
High Level Synthesis Tool
RTL
Logic Synthesis Tool
Bit-stream
Layout
Reconfigurable Unit
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High Level Synthesis
Behavioral Description
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The idea of Hls
HARDWARE COST Area minimization Power
minimization Configuration time minimization
Inter-DFG Resource Sharing Intra-DFG Resource
Sharing
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Stages of Traditional HLS
DFG
Operation Scheduling
Functional Unit Allocation
Register Allocation
Interconnection Binding
RTL
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Stages of Traditional HLS
Scheduling DFG
Allocation
Binding
DFG
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Reducing Resource usage In HLS
Trade-off between Hardware unit cost and
interconnection cost
Considering Hardware unit cost and
interconnection units cost altogether (Using
Integer Programming IP)
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High Level Synthesis
Data path Merging
Configuration Time Reduction By Data path Merging
Future Works (Possible Researches)
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Data path merging
An efficient HLS method for Inter-DFG resource
sharing
Making a single data path (Merged data path)
instead of multiple data path
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Optimizing Resource usage in data path merging
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Optimizing hardware cost in data path data path
merging
Using global resource sharing by Traditional
Synthesis
Using Integer Programming to merge DFGs
Merging DFGs one bye one by using Compatibility
Graph Method
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Data path merging bycompatibility graph method
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Minimizing cost in data path merging
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New data path merging method
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Design Space Exploration
Delay
Arch I
Arch II
Arch III
Hardware cost
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High Level Synthesis
Data path Merging
Configuration Time Reduction By Data path Merging
Future Works (Possible Researches)
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Creating Hardware in FPGA-based RTR systems
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Configuration Time
Configuration Time Transmitting Bit-streams to
FPGA loading the bit-streams into FPGA Average
configuration time size of the configuration
bit-streams / speed of the configuration
interface
Configuration Time Reduction Caching
Perfecting Compression/Decompression
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module total Config/Exe time
Module Number of kernels in the program
Configuration time Length of the bit-stream
clock frequency
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Configuration Time Reduction by data path
merging
Configuring merged data path instead of multiple
data path can reduce the module configuration
time
Merging a general purpose data path instead of
number of data paths
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Future works
Presenting new data path merging method to
optimize hardware cost Presenting new data path
merging method to reduce the configuration time
Using the merged data path in Call graph Using
the data path merging method to reduce the
on-line management overhead for the FPGA
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Future Works
Presenting New Data path merging methods to
optimize hardware cost Considering trade off
between intra-DFG similarity and inter-DFGs
similarity
Using the merged data path in Data graph
Using obtained merged data path in on-line
placement
Thanks