CDA 4150 Notes

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CDA 4150 Notes
Pipelining

• February 18, 2004
• By Nicholas Bray
• San Chong Cheng

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Matrices
How do we store A and B in a vector processor so
we can access the rows of A and the columns of B?
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Solution
M1
M2
M3
M4
Note this is not the best solution for computing
AxB C. cij a1jbi1 a2jbi2 a3jbi3
a4jbi4 So we would need to access akj and bik
in parallel. This can be done by switching the
rows of memory with the columns (we can access
all of Mi in parallel)
a11 a21 a31 a41 b11 b12 b13 b14
a12 a22 a32 a42 b21 b22 b23 b24
a13 a23 a33 a43 b31 b32 b33 b34
a14 a24 a34 a44 b41 b42 b43 b44
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(Review cont.)
How should we store the arrays, so that we can
access the matrix in parallel (rowscols of A and
B).
M1
M2
M3
M4
M5
a14 a23 a32 a41
a11 a34 a43
a13 a22 a31
a12 a21 a44
a24 a33 a42
The matrix can now access diagonally in parallel
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Pipelining Load Store
Instruction
Fetch
Execute
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2 Stages
Fetch Mar ? PC MDR ? MMAR
Fetch Unit Execute IR ? MDR PC
? PC 1
M1
MAR
IR
Exec A ? R1 B ? R2 ALU ? A (op) B C ? ALU
(results) R3 ? C
MDR
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Further Pipelining
Instruction
Fetch
ID / OF
Execute
ID / OF Instruction decode operand fetch
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3 Stages
Exec ALUop ? A (op) B C ? ALUop R3 ? C
Fetch Mar ? PC MDR ? MMAR IR ? MDR PC ? PC 1
ID / OF A ? R1 B ? R2
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4 Stages
Instruction
Fetch
ID / OF
Exec.
Write Back
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4 Stages in RTN
Exec ALUop ? A (op) B C ? ALUop
Fetch Mar ? PC MDR ? MMAR IR ? MDR PC ? PC 1
WB R3 ? C
ID / OF A ? R1 B ? R2
could have conflict with OF and Exec or Exec and
WB
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4 Stages Example
Register Files
V3 V1 V2
There is a conflict in OF and WB because both are
trying to access the register files
R3 V3
I. M. IF
OF
EXEC.
WB
M
OF
WB
MAR
PC
MDR
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5 Stages
Inst.
Fetch
ID / OF
Exec.
Mem
WB
Inst. Memory
Data Memory
Register File
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Load (5 stages)
Load Reg, Adrr
ID / OF
Exec
Mem
WB
IF
Inst.
Fetch
Get values from Registers File
Might Need To Offset
Gets Value FromData Mem.
Write Value back To Reg.
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Add (5 stages)
ADD R3, R1, R2
IF
ID / OF
Exec
Mem
WB
Inst.
Fetch
V1 R1 V2 R2
V3 gets V1 V2
R3 Gets V3
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Store (5 stages)
STORE Adrr, Reg
ID / OF
Exec
Mem
WB
IF
Inst.
Fetch
V1 Gets Reg
Calculate Effective Address
Adrr Gets V1
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Bernsteins Conditions(Review)
If input(S1) n output(S2) ØØ
(antidependency WAR) and input(S2) n output(S1)
Ø Ø(data dependency RAW) and output(S1) n
output(S2) Ø (output dependency WAW) Then S1
S2
WAR Write After Read RAW Read After Write WAW
Write After Write