Tufan Karalar, Farinaz Koushanfar, Huifang Qin

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Comparison of Techniques to Reduce the VLSI
Standby Leakage Power
EE241 Project Final Presentation

• Tufan Karalar, Farinaz Koushanfar, Huifang Qin
• tufan,farinaz,huifangq_at_eecs.berkeley.edu

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Motivation Problem Statement

• Portable appliances- Today
• Speed?, performance ?, power constraints?
• Sensor Networks- Future
• BWRC PicoRadio ultra low power ? ?, low speed ?
  ?, duty cycles? ?(1),
• Standby is the dominant mode of operation
• Power supplies ?, feature size ?, Vth ?

BUT! Decreasing the Vth will exponentially
increase the standby sub-threshold leakage
current standby leakage power consumption!
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Proposed Solutions From the Literature

• Device Technology
• SOI (in particular SIMOX)
• Bulk modification
• Boosted gate MOS (BGMOS)

• Circuit Configuration Techniques
• Power switch control MTCMOS, SCCMOS,
• Triple-s or smart series switch, IPS, VRC
• Substrate biasing VTMOS, DTMOS

Our goal in this project is to study alternative
approaches for low leakage power compare them
in terms of their advantages/disadvantages
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Assumptions on our block, simulation/analysis

• Layout 8-bit counter/frequency divider
• ST 0.18? dual threshold technology
• Cadence Arcadia flow? Spectre netlist for
  fast/slow/typical process models

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State preservation study while ramping supply
voltage down

• Previous approach
• Adding memory cell
• Using Smart Series Switch
• Intermittent Power Supply
• Our approach
• Using minimum Vdd in MTCMOS circuit to preserve
  the state
• Our approach
• Constraints in this approach
• Minimum Vdd
• Maximum ramping up and ramping down slope
• Circuit sleep time

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How does sequential circuit lose states
After the supply is fully turned off, the counter
outputs all keep the previous state.
After the supply is fully turned off, the counter
outputs all lose state.
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How does sequential circuit lose states (contd)
The VTC of the inverter loop in the flip-flop
determines the state preserving. (The inverter
characteristic VTC distorted when Vddlt100mv.)
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Minimum Vdd constraint
Minimum Vdd to preserve state in different
process and with different temperature
The inverter loop state changing.
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Ramping down slope constraint
Vdd_min95mv when down slope 1V/0.01ms
Vdd_min91mv when down slope 1V/0.5ms
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Ramping up slope constraint
Maximum ramping up slope is about 1V/15ns
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Circuit Sleep Time effects the Ramping Up Slope
When sleep time is long enough (gt100us), the max
ramping up slope is 1.1V/13ns. When sleep time
is 1us, the max ramping up slope is 1.1v/9ns.
When sleep time is 1ns, there is no max
ramping up slope constraint.
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Notes on Supply Ramping Analysis
The technique of ramping the supply voltage to
a virtual vdd value in the standby mode can
preserving the states, while meeting the
constraints of minimum standby mode Vdd, maximum
down and up slope, with the maximum up slope
depended by the sleep time.   But for our real
design, the vdd up and down slope is far more
larger than the limit of around 1V/10ns, which
is acturally around 1V/10us. So we dont need to
really concern about these two constraints.  
Next we study MTCMOS to see how much power saving
can this technique provide us while the states
are preserved. The power switch is sized to make
the virtual vdd stays at vddmin 50mV.
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Nominal Leakage Power

• Observed when theres no switching activity in
  circuit.
• Current Leaking through the supply switches.
• Leakage Strong Function of
• Temperature
• Process
• Supply
• Input pattern

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Leakage Improvement UsingMTCMOS

• Leakage Power improvement can be as high as 50x
• High Vt devices need to be sized too large
  (5-6mm) to attain the low Stand by Vdd
  requirement.
• This large supply switch requirement for such a
  small block makes high Vth switches impractical

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Improvement using MTCMOS (contd)
Supply Switch

• Required minimum supply switch sizes (for low Vth
  switches) to achieve the levels of leakage
  savings.

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COST of MTCMOS

• Leakage Power saving is not for free.
• You pay for it (sort of) in delay.
• Each control factor, adds 10 more on the delay.
• In worst case we get a delay degradation of 30
• With the orders of reduction in leakage current,
  its favorable to use supply switch devices.

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Substrate Biasing
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CONCLUSIONS

• MTCMOS can both preserve state and reduce leakage
  by as much as 50x.
• It adds a delay of 30
• But high Vth switches are too large to be
  practical
• Low Vth switches are more feasible.
• Substrate biasing can also achieve some savings
  but as gammas scale down with technology they
  dont have a bright future!
• All of the presently proposed techniques are very
  process/temperature dependent