CS4100: Instruction Set Architecture

1
CS4100 ?????Instruction Set Architecture

• Adapted from class notes of D. Patterson and W.
  Dally

2
Outline

• Instruction set architecture(using MIPS ISA as
  an example)
• Operands
• Register operands and their organization
• Memory operands, data transfer
• Immediate operands
• Signed and Unsigned Numbers
• Instruction format
• Operations
• Arithmetic and logical
• Decision making and branches
• Jumps for procedures
• Addressing modes
• Comparison with other ISAs

3
What Is Computer Architecture?

• Computer Architecture Instruction Set
  Architecture Machine Organization
• ... the attributes of a computing system as
  seen by the ____________ language programmer,
  i.e. the conceptual structure and functional
  behavior

assembly
What are specified?
4
Things In Assembly

• C code a b 5
• load r1, Mb
• load r2, 5
• add r3, r1, r2
• store r3, Ma

Operator (op code)
5
Instruction Set Architecture

• Instructions Language of the Machine
• ISA specifies
• Operations
• data movement, arithmetic, logical, shift/rotate,
  conversion, input/output, control, and system
  calls
• Data types
• bit, byte, bit field, signed/unsigned integers,
  logical, floating point, character
• of operands and addressing mode
• 3, 2, 1, or 0 operands constant, from register
  or from memory
• Registers
• integer, floating point, control
• Instruction representation as bit strings

6
MIPS ISA as an Example
Registers

• Instruction categories
• Load/Store
• Computational
• Jump and Branch
• Floating Point
• Memory Management
• Special

r0 - r31
PC
HI
LO
3 Instruction Formats all 32 bits wide
OP
rs
rd
sa
funct
rt
OP
rs
immediate
rt
jump target
OP
7
Outline

• Instruction set architecture(using MIPS ISA as
  an example)
• Operands (Sec. 2.3)
• Register operands and their organization
• Memory operands, data transfer
• Immediate operands
• Signed and Unsigned Numbers
• Instruction format
• Operations
• Arithmetic and logical
• Decision making and branches
• Jumps for procedures
• Addressing modes
• Comparison with other ISAs

8
MIPS Instruction Set Architecture

• Used as the example throughout the book
• Stanford MIPS commercialized by MIPS Technologies
  (www.mips.com)
• Large share of embedded core market
• Applications in consumer electronics,
  network/storage equipment, cameras, printers,
• Typical of many modern ISAs
• See MIPS Reference Data tear-out card, and
  Appendixes B and E

9
Arithmetic Operations

• Add and subtract, three operands
• Two sources and one destination
• add a, b, c a gets b c
• All arithmetic operations have this form
• Design Principle 1 Simplicity favours regularity
• Regularity makes implementation simpler
• Simplicity enables higher performance at lower
  cost

10
Register Operands

• Unlike high-level language, assembly doesnt use
  variablesgt assembly operands are registers
• Limited number of special locations built
  directly into the hardware
• Operations are performed on them
• Benefits
• Registers in hardware gt faster than memory
• Registers are easier for a compiler to use
• e.g., as a place for temporary storage
• Registers can hold variables to reduce memory
  traffic and improve code density (since register
  named with fewer bits than memory location)

11
Arithmetic Example

• How to do the following C statement (f, , j in
  s0, , s4)?
• f (g h) - (i j)
• Compiled MIPS codes
• add s0,s1,s2 f g h
• add t0,s3,s4 t0 i j
• sub s0,s0,t0 f(gh)-(ij)
• Intermediate temporary register t0 used

12
MIPS Registers

• 32 registers, each is 32 bits wide
• 32-bit data called a word
• Registers are numbered from 0 to 31
• Each can be referred to by number or name
• Number references
• 0, 1, 2, 30, 31
• By convention, each register also has a name to
  make it easier to code, e.g.,
• 16 - 23 ? s0 - s7 (C variables)
• 8 - 15 ? t0 - t7 (temporary)
• 32 FP 32-bit registers (paired for double
  precision)
• Others HI, LO, PC
• Design Principle 2 Smaller is faster
• c.f. main memory millions of locations

13
MIPS R2000 Organization
Fig. A.10.1
14
Operations of Hardware

• Syntax of basic MIPS arithmetic/logic
  instructions
• 1 2 3 4
• add s0,s1,s2 f g h
• 1) operation by name
• 2) operand getting result (destination)
• 3) 1st operand for operation (source1)
• 4) 2nd operand for operation (source2)
• Each instruction is 32 bits
• Syntax is rigid 1 operator, 3 operands
• Why? Keep hardware simple via regularity

15
Register Architecture

• Accumulator (1 register)
• 1 address add A acc ? acc memA
• 1x address addx A acc ? acc memAx
• Stack
• 0 address add tos ? tos next
• General Purpose Register
• 2 address add A,B EA(A) ? EA(A)
  EA(B)
• 3 address add A,B,C EA(A) ? EA(B)
  EA(C)
• Load/Store (a special case of GPR)
• 3 address add ra,rb,rc ra ? rb rc
• load ra,rb ra ? memrb
• store ra,rb memrb ? ra

16
Register Organization Affects Programming

• Code for C A B for four register
  organizations
• Stack Accumulator Register Register
• (reg-mem) (load-store)
• Push A Load A Load r1,A Load r1,A
• Push B Add B Add r1,B Load r2,B
• Add Store C Store C,r1 Add r3,r1,r2
• Pop C Store C,r3
• gt Register organization is an attribute of ISA!
• Comparison Byte per instruction? Number of
  instructions? Cycles per instruction?
• Since 1975 all machines use GPRs

17
Outline

• Instruction set architecture(using MIPS ISA as
  an example)
• Operands (Sec. 2.3)
• Register operands and their organization
• Memory operands, data transfer
• Immediate operands
• Signed and Unsigned Numbers
• Instruction format
• Operations
• Arithmetic and logical
• Decision making and branches
• Jumps for procedures
• Addressing modes
• Comparison with other ISAs

18
Memory Operands

• C variables map onto registers what about large
  data structures like arrays?
• Memory contains such data structures
• But MIPS arithmetic instructions operate on
  registers, not directly on memory
• Data transfer instructions (lw, sw, ...) to
  transfer between memory and register
• Memory is byte addressed
• Each address identifies an 8-bit byte
• Words are aligned in memory
• Word address must be a multiple of 4
• Memory0, Memory4, Memory8,
• MIPS is Big Endian
• Most-significant byte at least address of a word

8
4

word
0
memory
19
Memory Operand Example 1

• C code
• g h A8
• g in s1, h in s2, base address of A in s3
• Compiled MIPS code
• Index 8 requires offset of 32
• 4 bytes per word
• lw t0, 32(s3) load wordadd s1, s2, t0

offset
base register
20
Memory Operand Example 2

• C code
• A12 h A8
• h in s2, base address of A in s3
• Compiled MIPS code

21
MIPS Data Transfer Instructions

• Instruction Comment
• sw t3,500(t4) Store word
• sh t3,502(t2) Store half
• sb t2,41(t3) Store byte
• lw t1, 30(t2) Load word
• lh t1, 40(t3) Load halfword
• lhu t1, 40(t3) Load halfword unsigned
• lb t1, 40(t3) Load byte
• lbu t1, 40(t3) Load byte unsigned
• lui t1, 40 Load Upper Immediate (16 bits
  shifted left by 16)

22
Load Byte Signed/Unsigned
F7
F7
F7
Sign-extended
FFFFFF

• lb t1, 0(t0)

lbu t2, 0(t0)
F7
000000
Zero-extended
23
Registers vs. Memory

• Registers are faster to access than memory
• Operating on memory data requires loads and
  stores
• More instructions to be executed
• Compiler must use registers for variables as much
  as possible
• Only spill to memory for less frequently used
  variables
• Register optimization is important!

24
Outline

• Instruction set architecture(using MIPS ISA as
  an example)
• Operands (Sec 2.3)
• Register operands and their organization
• Memory operands, data transfer, and addressing
• Immediate operands
• Signed and Unsigned Numbers
• Instruction format
• Operations
• Arithmetic and logical
• Decision making and branches
• Jumps for procedures
• Addressing modes
• Comparison with other ISAs

25
Constants

• Small constants used frequently (50 of operands)
  e.g., A A 5 B B 1 C C - 18
• MIPS Instructions addi 29, 29, 4 slti 8,
  18, 10 andi 29, 29, 6 ori 29, 29, 4
• Design Principle 3 Make the common case fast
• Immediate operand avoids a load instruction
• No subtract immediate instruction
• Just use a negative constant
• addi s2, s1, -1

26
Immediate Operands

• Immediate numerical constants
• Often appear in code, so there are special
  instructions for them
• Add Immediate
• f g 10 (in C)
• addi s0,s1,10 (in MIPS)
• where s0,s1 are associated with f,g
• Syntax similar to add instruction, except that
  last argument is a number instead of a register
• One particular immediate, the number zero (0),
  appears very often in code so we define register
  zero (0 or zero) to always 0
• This is defined in hardware, so an instruction
  like
• addi 0,0,5 will not do anything

27
Outline

• Instruction set architecture(using MIPS ISA as
  an example)
• Operands
• Register operands and their organization
• Memory operands, data transfer
• Immediate operands
• Signed and Unsigned Numbers (Sec. 2.4)
• Instruction format (Sec. 2.5. 2.10)
• Operations
• Arithmetic and logical
• Decision making and branches
• Jumps for procedures
• Addressing modes
• Comparison with other ISAs

28
Unsigned Binary Integers

• Given an n-bit number

• Range 0 to 2n 1
• Example
• 0000 0000 0000 0000 0000 0000 0000 10112 0
  123 022 121 120 0 8 0 2 1
  1110
• Using 32 bits
• 0 to 4,294,967,295

29
2s-Complement Signed Integers

• Given an n-bit number

• Range 2n 1 to 2n 1 1
• Example
• 1111 1111 1111 1111 1111 1111 1111 11002 1231
  1230 122 021 020 2,147,483,648
  2,147,483,644 410
• Using 32 bits
• 2,147,483,648 to 2,147,483,647

30
2s-Complement Signed Integers

• Bit 31 is sign bit
• 1 for negative numbers
• 0 for non-negative numbers
• (2n 1) cant be represented
• Non-negative numbers have the same unsigned and
  2s-complement representation
• Some specific numbers
• 0 0000 0000 0000
• 1 1111 1111 1111
• Most-negative 1000 0000 0000
• Most-positive 0111 1111 1111

31
Signed Negation

• Complement and add 1
• Complement means 1 ? 0, 0 ? 1

• Example negate 2
• 2 0000 0000 00102
• 2 1111 1111 11012 1 1111 1111
  11102

32
Sign Extension

• Representing a number using more bits
• Preserve the numeric value
• In MIPS instruction set
• addi extend immediate value
• lb, lh extend loaded byte/halfword
• beq, bne extend the displacement
• Replicate the sign bit to the left
• c.f. unsigned values extend with 0s
• Examples 8-bit to 16-bit
• 2 0000 0010 gt 0000 0000 0000 0010
• 2 1111 1110 gt 1111 1111 1111 1110

33
Outline

• Instruction set architecture(using MIPS ISA as
  an example)
• Operands
• Register operands and their organization
• Memory operands, data transfer
• Immediate operands
• Signed and Unsigned Numbers
• Instruction format (Sec. 2.5)
• Operations
• Arithmetic and logical
• Decision making and branches
• Jumps for procedures
• Addressing modes
• Comparison with other ISAs

34
Representing Instructions

• Currently we only work with words (32-bit
  blocks)
• Each register is a word
• lw and sw both access memory one word at a time
• So how do we represent instructions?
• Remember Computer only understands 1s and 0s, so
  add t0,0,0 is meaningless to hardware
• Instructions are encoded in binary (called
  machine code)
• MIPS wants simplicity since data is in words,
  make instructions in words

35
MIPS Instruction Format

• MIPS instructions
• Encoded as 32-bit instruction words
• Divide instruction word into fields
• Each field tells something about instruction
• We could define different fields for each
  instruction, but MIPS is based on simplicity, so
  define 3 basic types of instruction formats
• R-format for register
• I-format for immediate, and lw and sw (since the
  offset counts as an immediate)
• J-format for jump

36
R-format Instructions (1/2)

• Instruction fields
• opcode operation code (Note 0 for all R-Format
  instructions)
• funct function code (extends opcode)
• Question Why arent opcode and funct a single
  12-bit field?
• rs first source register number
• rt second source register number
• rd destination register number
• shamt shift amount

37
R-Format Instructions (2/2)

• Notes about register fields
• Each register field is exactly 5 bits, which
  means that it can specify any unsigned integer in
  the range 0-31. Each of these fields specifies
  one of the 32 registers by number.
• Final field
• shamt contains the amount a shift instruction
  will shift by. Shifting a 32-bit word by more
  than 31 is useless, so this field is only 5 bits
• This field is set to 0 in all but the shift
  instructions

38
R-Format Example

• MIPS Instruction
• add 8,9,10
• opcode 0 (look up in table)
• funct 32 (look up in table)
• rs 9 (first operand)
• rt 10 (second operand)
• rd 8 (destination)
• shamt 0 (not a shift)

binary representation
called a Machine Language Instruction
39
I-format Instructions

• Immediate arithmetic and load/store instructions
• opcode uniquely specifies an I-format
  instruction
• rs/rt source/target register number
• Constant 215 to 215 1
• Offset offset added to base address in rs
• Key concept Only one field is inconsistent with
  R-format. Most importantly, opcode is still in
  same location

40
I-Format Example 1

• MIPS Instruction
• addi 21,22,-50
• opcode 8 (look up in table)
• rs 22 (register containing operand)
• rt 21 (target register)
• immediate -50 (by default, this is decimal)

decimal representation
binary representation
41
I-Format Example 2

• MIPS Instruction
• lw t0,1200(t1)
• opcode 35 (look up in table)
• rs 9 (base register)
• rt 8 (target register)
• immediate 1200 (offset)

decimal representation
binary representation
42
I-Format Problem

• What if immediate is too big to fit in immediate
  field?
• Load Upper Immediate
• lui register, immediate
• puts 16-bit immediate in upper half (high order
  half) of the specified register, and sets lower
  half to 0s
• addi t0,t0, 0xABABCDCD
• becomes
• lui at, 0xABAB ori at, at,
  0xCDCD add t0,t0,at

43
Big Idea Stored Program Concept

• Computers built on 2 key principles (John Von
  Neumann)
• Instructions are represented as numbers
• Programs are stored in memory
• to be read or written just like data
• Fetch Execute Cycle
• Instructions are fetched and put into a special
  register
• Bits in the register "control" the subsequent
  actions
• Fetch the next instruction and continue

memory for data, programs, compilers, editors,
etc.
44
Outline

• Instruction set architecture(using MIPS ISA as
  an example)
• Operands
• Register operands and their organization
• Memory operands, data transfer, and addressing
• Immediate operands
• Signed and Unsigned Numbers
• Instruction format
• Operations
• Arithmetic and logical (Sec 2.6)
• Decision making and branches
• Jumps for procedures
• Addressing modes
• Comparison with other ISAs

45
MIPS Arithmetic Instructions

• Instruction Example Meaning
  Comments
• add add 1,2,3 1 2 3
  3 operands
• subtract sub 1,2,3 1 2 - 3
  3 operands
• add immediate addi 1,2,100 1 2 100
  constant

46
Bitwise Operations

• Up until now, weve done arithmetic (add, sub,
  addi) and memory access (lw and sw)
• All of these instructions view contents of
  register as a single quantity (such as a signed
  or unsigned integer)
• New perspective View contents of register as 32
  bits rather than as a single 32-bit number
• Since registers are composed of 32 bits, we may
  want to access individual bits rather than the
  whole.
• Introduce two new classes of instructions
• Logical Operators
• Shift Instructions

47
Logical Operations

• Instructions for bitwise manipulation

• Useful for extracting and inserting groups of
  bits in a word

48
Logical Instructions

• 1 2 3 4
• or t0, t1, t2
• 1) operation name
• 2) register that will receive value
• 3) first operand (register)
• 4) second operand (register) or immediate
  (numerical constant)
• Instruction names
• and, or expect the third argument to be a
  register
• andi, ori expect the third argument to be
  immediate
• MIPS Logical Operators are all bitwise, meaning
  that bit 0 of the output is produced by the
  respective bit 0s of the inputs, bit 1 by the
  bit 1s, etc.

49
AND Operations

• Useful to mask bits in a word
• Select some bits, clear others to 0
• and t0, t1, t2

0000 0000 0000 0000 0000 1101 1100 0000
t2
0000 0000 0000 0000 0011 1100 0000 0000
t1
0000 0000 0000 0000 0000 1100 0000 0000
t0
50
OR Operations

• Useful to include bits in a word
• Set some bits to 1, leave others unchanged
• or t0, t1, t2

0000 0000 0000 0000 0000 1101 1100 0000
t2
0000 0000 0000 0000 0011 1100 0000 0000
t1
0000 0000 0000 0000 0011 1101 1100 0000
t0
51
Shift Instructions (1/3)

• 1 2 3 4
• sll t2,s0,4 1) operation name
• 2) register that will receive value
• 3) first operand (register)
• 4) shift amount (constant)
• MIPS has three shift instructions
• sll (shift left logical) shifts left, fills
  empties with 0s
• srl (shift right logical) shifts right, fills
  empties with 0s
• sra (shift right arithmetic) shifts right, fills
  empties by sign extending

52
Shift Instructions (2/3)

• Move (shift) all the bits in a word to the left
  or right by a number of bits, filling the emptied
  bits with 0s.
• Example shift right by 8 bits
• 0001 0010 0011 0100 0101 0110 0111 1000
• 0000 0000 0001 0010 0011 0100 0101 0110
• Example shift left by 8 bits
• 0001 0010 0011 0100 0101 0110 0111 1000
• 0011 0100 0101 0110 0111 1000 0000 0000

53
Shift Instructions (3/3)

• Example shift right arithmetic by 8 bits
• 0001 0010 0011 0100 0101 0110 0111 1000
• 0000 0000 0001 0010 0011 0100 0101 0110
• Example shift right arithmetic by 8 bits
• 1001 0010 0011 0100 0101 0110 0111 1000
• 1111 1111 1001 0010 0011 0100 0101 0110

54
Uses for Shift Instructions (1/2)

• Suppose we want to get byte 1 (bit 15 to bit 8)
  of a word in t0. We can use sll
  t0,t0,16 srl t0,t0,24
• 0001 0010 0011 0100 0101 0110 0111 1000
• 0101 0110 0111 1000 0000 0000 0000 0000
• 0000 0000 0000 0000 0000 0000 0101 0110

55
Uses for Shift Instructions (2/2)

• Shift for multiplication in binary
• Multiplying by 4 is same as shifting left by 2
• 112 x 1002 11002
• 10102 x 1002 1010002
• Multiplying by 2n is same as shifting left by n
• Since shifting is so much faster than
  multiplication (you can imagine how complicated
  multiplication is), a good compiler usually
  notices when C code multiplies by a power of 2
  and compiles it to a shift instruction
• a 8 (in C)
• would compile to
• sll s0,s0,3 (in MIPS)

56
MIPS Logical Instructions

• Instruction Example Meaning Comment
• and and 1,2,3 1 2 3 3 reg. operands
  Logical AND
• or or 1,2,3 1 2 3 3 reg. operands
  Logical OR
• nor nor 1,2,3 1 (2 3) 3 reg. operands
  Logical NOR
• and immediate andi 1,2,10 1 2 10 Logical
  AND reg, zero exten.
• or immediate ori 1,2,10 1 2 10 Logical OR
  reg, zero exten.
• shift left logical sll 1,2,10 1 2 ltlt
  10 Shift left by constant
• shift right logical srl 1,2,10 1 2 gtgt
  10 Shift right by constant
• shift right arithm. sra 1,2,10 1 2 gtgt
  10 Shift right (sign extend)

57
So Far...

• All instructions have allowed us to manipulate
  data.
• So weve built a calculator.
• In order to build a computer, we need ability to
  make decisions

58
Outline

• Instruction set architecture(using MIPS ISA as
  an example)
• Operands
• Register operands and their organization
• Memory operands, data transfer, and addressing
• Immediate operands
• Signed and Unsigned Numbers
• Instruction format
• Operations
• Arithmetic and logical
• Decision making and branches (Sec. 2.7)
• Jumps for procedures
• Addressing modes
• Comparison with other ISAs

59
MIPS Decision Instructions

• beq register1, register2, L1
• Decision instruction in MIPS
• beq register1, register2, L1Branch if
  (registers are) equal meaning if
  (register1register2) goto L1
• Complementary MIPS decision instruction
• bne register1, register2, L1Branch if
  (registers are) not equal meaning if
  (register1!register2) goto L1
• These are called conditional branches

60
MIPS Goto Instruction

• j label
• MIPS has an unconditional branch
• j label
• Called a Jump Instruction jump directly to the
  given label without testing any condition
• meaning goto label
• Technically, its the same as
• beq 0,0,label
• since it always satisfies the condition
• It has the j-type instruction format

61
Compiling C if into MIPS

• Compile by hand
• if (i j) fgh else fg-h
• Use this mapping
• f s0, g s1, h s2,i s3, j s4
• Final compiled MIPS code
• beq s3,s4,True branch ij sub s0,s1,
  s2 fg-h(false) j Fin go to
  FinTrue add s0,s1,s2 fgh (true)Fin
• Note Compiler automatically creates labels to
  handle decisions (branches) appropriately

62
Inequalities in MIPS

• Until now, weve only tested equalities ( and
  ! in C), but general programs need to test lt and
  gt
• Set on Less Than
• slt reg1,reg2,reg3
• meaning
• if (reg2 lt reg3) reg1 1 set else
  reg1 0 reset
• Compile by hand if (g lt h) goto LessLet g
  s0, h s1
• slt t0,s0,s1 t0 1 if glth bne
  t0,0,Less goto Less if t0!0
• MIPS has no branch on less than gt too complex

63
Immediate in Inequalities

• There is also an immediate version of slt to
  test against constants slti
• if (g gt 1) goto Loop
• Loop . . .
• slti t0,s0,1 t0 1 if s0lt1 (glt1)beq
  t0,0,Loop goto Loop if t00
• Unsigned inequality sltu, sltiu
• s0 FFFF FFFAhex, s1 0000 FFFAhex
• slt t0, s0, s1 gt t0 ?sltu t1, s0,
  s1 gt t1 ?

C
MIPS
64
Outline

• Instruction set architecture(using MIPS ISA as
  an example)
• Operands
• Register operands and their organization
• Immediate operands
• Memory operands, data transfer, and addressing
• Signed and Unsigned Numbers
• Instruction format
• Operations
• Arithmetic and logical
• Decision making and branches
• Jumps for procedures (Sec. 2.8)
• Addressing modes
• Comparison with other ISAs

65
Procedure Call

• Steps required
• Place parameters in registers
• Transfer control to procedure
• Acquire storage for procedure
• Perform procedures operations
• Place result in register for caller
• Return to place of call

66
C Function Call Bookkeeping

• ... sum(a,b)... / as0 bs1 /
• int sum(int x, int y) return xy
• Return address ra
• Procedure address Labels
• Arguments a0, a1, a2, a3
• Return value v0, v1
• Local variables s0, s1, , s7
• Note the use of register conventions

67
Registers Conventions for MIPS
0 zero constant 0 1 at reserved for
assembler 2 v0 expression evaluation
3 v1 function results 4 a0 arguments 5 a1 6 a2 7
a3 8 t0 temporary caller saves . . . 15 t7
16 s0 callee saves . . . 23 s7 24 t8 temporary
(contd) 25 t9 26 k0 reserved for OS
kernel 27 k1 28 gp pointer to global
area 29 sp stack pointer 30 fp frame
pointer 31 ra return address
Fig. 2.18
68
Instruction Support for Functions

• ... sum(a,b)... / as0 bs1 /
• int sum(int x, int y) / xa0 ya1
  / return xy
• address1000 add a0,s0,zero x lt a1004
  add a1,s1,zero y lt b 1008 addi
  ra,zero,1016 ra lt 10161012 j sum
  jump to sum1016 ...
• 2000 sum add v0,a0,a12004 jr ra new
  instruction

C
MIPS
69
JAL and JR

• Single instruction to jump and save return
  address jump and link (jal)
• Replace1008 addi ra,zero,1016 ra10161012
  j sum go to sum
• with1012 jal sum ra1016,go to sum
• Step 1 (link) Save address of next instruction
  into ra
• Step 2 (jump) Jump to the given label
• Why have a jal? Make the common case fast
  functions are very common
• jump register jr register
• jr provides a register that contains an address
  to jump to usually used for procedure return

70
Leaf Procedure Example

• C code
• int leaf_example (int g, h, i, j) int f f
  (g h) - (i j) return f
• Arguments g, , j in a0, , a3
• f in s0 (hence, need to save s0 on stack)
• Result in v0
• MIPS code
• leaf_example addi sp, sp, -4 sw s0,
  0(sp) add t0, a0, a1 add t1, a2, a3
  sub s0, t0, t1 add v0, s0, zero lw
  s0, 0(sp) addi sp, sp, 4 jr ra

Save s0 on stack
Procedure body
Result
Restore s0
Return
71
C Memory Allocation
Address

0
72
Non-Leaf Procedures

• Procedures that call other procedures
• For nested call, caller needs to save on the
  stack
• Its return address
• Any arguments and temporaries needed after the
  call
• Restore from the stack after the call

73
Non-Leaf Procedure Example

• C code
• int fact (int n) if (n lt 1) return f
  else return n fact(n - 1)
• Argument n in a0
• Result in v0

74
Non-Leaf Procedure Example

• MIPS code
• fact addi sp, sp, -8 adjust stack
  for 2 items sw ra, 4(sp) save
  return address sw a0, 0(sp) save
  argument slti t0, a0, 1 test for n lt
  1 beq t0, zero, L1 addi v0, zero, 1
  if so, result is 1 addi sp, sp, 8
  pop 2 items from stack jr ra
  and returnL1 addi a0, a0, -1
  else decrement n jal fact
  recursive call lw a0, 0(sp)
  restore original n lw ra, 4(sp)
  and return address addi sp, sp, 8
  pop 2 items from stack mul v0, a0, v0
  multiply to get result jr ra
  and return

75
Outline

• Instruction set architecture(using MIPS ISA as
  an example)
• Operands
• Register operands and their organization
• Immediate operands
• Memory operands, data transfer, and addressing
• Signed and Unsigned Numbers
• Instruction format
• Operations
• Arithmetic and logical
• Decision making and branches
• Jumps for procedures (Sec. 2.8)
• Addressing modes (Sec. 2.10)
• Comparison with other ISAs

76
Branch Addressing

• Branch instructions specify
• Opcode, two registers, target address
• I-format
• Most branch targets are near branch
• Forward or backward

• PC-relative addressing
• Relative to PC4 (addr of following instruction)
• Target address (PC4) offset 4

77
Jump Addressing

• Jump (j and jal) targets could be anywhere in
  text segment
• Encode full address in instruction

• J-format
• (Pseudo)Direct jump addressing
• Target address PC3128 (address 4)

78
Target Addressing Example

• Loop code from earlier example
• Assume Loop at location 80000

79
Branching Far Away

• If branch target is too far to encode with 16-bit
  offset, assembler rewrites the code
• Example
• beq s0,s1, L1
• ?
• bne s0,s1, L2 j L1L2

80
Addressing Mode Summary
81
Synchronization

• Two processors sharing an area of memory
• P1 writes, then P2 reads
• Data race if P1 and P2 dont synchronize
• Result depends of order of accesses
• Hardware support required
• Atomic read/write memory operation
• No other access to the location allowed between
  the read and write
• Could be a single instruction
• E.g., atomic swap of register ? memory
• Or an atomic pair of instructions

82
Synchronization in MIPS

• Load linked ll rt, offset(rs)
• Store conditional sc rt, offset(rs)
• Succeeds if location not changed since the ll
• Returns 1 in rt
• Fails if location is changed
• Returns 0 in rt
• Example atomic swap (to test/set lock variable)
• try add t0,zero,s4 copy exchange value
• ll t1,0(s1) load linked
• sc t0,0(s1) store conditional
• beq t0,zero,try branch store fails
• add s4,zero,t1 put load value in s4

83
Summary MIPS ISA (1/2)

• 32-bit fixed format instructions (3 formats)
• 32 32-bit GPR (R0 zero), 32 FP registers, (and
  HI LO)
• partitioned by software convention
• 3-address, reg-reg arithmetic instructions
• Memory is byte-addressable with a single
  addressing mode basedisplacement
• 16-bit immediate plus LUI
• Decision making with conditional branches beq,
  bne
• Often compare against zero or two registers for
• To help decisions with inequalities, use Set on
  Less Thancalled slt, slti, sltu, sltui
• Jump and link puts return address PC4 into link
  register (R31)
• Branches and Jumps were optimized to address to
  words, for greater branch distance

84
Summary MIPS ISA (2/2)

• Immediates are extended as follows
• logical immediate zero-extended to 32 bits
• arithmetic immediate sign-extended to 32 bits
• Data loaded by lb and lh are similarly
  extendedlbu, lhu are zero extended lb, lh are
  sign extended
• Simplifying MIPS Define instructions to be same
  size as data (one word), so they can use same
  memory
• Stored Program Concept Both data and actual code
  (instructions) are stored in the same memory
• Instructions formats are kept as similar as
  possible

85
Outline

• Instruction set architecture(using MIPS ISA as
  an example)
• Operands
• Register operands and their organization
• Immediate operands
• Memory operands, data transfer, and addressing
• Signed and Unsigned Numbers
• Instruction format
• Operations
• Arithmetic and logical
• Decision making and branches
• Jumps for procedures (Sec. 2.8)
• Addressing modes
• Comparison with other ISAs (Sec. 2.16-17)

86
ARM MIPS Similarities

• ARM the most popular embedded core
• Similar basic set of instructions to MIPS

87
Compare and Branch in ARM

• Uses condition codes for result of an
  arithmetic/logical instruction
• Negative, zero, carry, overflow
• Compare instructions to set condition codes
  without keeping the result
• Each instruction can be conditional
• Top 4 bits of instruction word condition value
• Can avoid branches over single instructions

88
Instruction Encoding
89
The Intel x86 ISA

• Evolution with backward compatibility
• 8080 (1974) 8-bit microprocessor
• Accumulator, plus 3 index-register pairs
• 8086 (1978) 16-bit extension to 8080
• Complex instruction set (CISC)
• 8087 (1980) floating-point coprocessor
• Adds FP instructions and register stack
• 80286 (1982) 24-bit addresses, MMU
• Segmented memory mapping and protection
• 80386 (1985) 32-bit extension (now IA-32)
• Additional addressing modes and operations
• Paged memory mapping as well as segments

90
The Intel x86 ISA

• Further evolution
• i486 (1989) pipelined, on-chip caches and FPU
• Compatible competitors AMD, Cyrix,
• Pentium (1993) superscalar, 64-bit datapath
• Later versions added MMX (Multi-Media eXtension)
  instructions
• The infamous FDIV bug
• Pentium Pro (1995), Pentium II (1997)
• New microarchitecture (see Colwell, The Pentium
  Chronicles)
• Pentium III (1999)
• Added SSE (Streaming SIMD Extensions) and
  associated registers
• Pentium 4 (2001)
• New microarchitecture
• Added SSE2 instructions

91
The Intel x86 ISA

• And further
• AMD64 (2003) extended architecture to 64 bits
• EM64T Extended Memory 64 Technology (2004)
• AMD64 adopted by Intel (with refinements)
• Added SSE3 instructions
• Intel Core (2006)
• Added SSE4 instructions, virtual machine support
• AMD64 (announced 2007) SSE5 instructions
• Intel declined to follow, instead
• Advanced Vector Extension (announced 2008)
• Longer SSE registers, more instructions
• If Intel didnt extend with compatibility, its
  competitors would!
• Technical elegance ? market success

92
Basic x86 Registers
93
Basic x86 Addressing Modes

• Two operands per instruction

• Memory addressing modes
• Address in register
• Address Rbase displacement
• Address Rbase 2scale Rindex (scale 0, 1,
  2, or 3)
• Address Rbase 2scale Rindex displacement

94
x86 Instruction Encoding

• Variable length encoding
• Postfix bytes specify addressing mode
• Prefix bytes modify operation
• Operand length, repetition, locking,

95
Fallacies

• Powerful instruction ? higher performance
• Fewer instructions required
• But complex instructions are hard to implement
• May slow down all instructions, including simple
  ones
• Compilers are good at making fast code from
  simple instructions
• Use assembly code for high performance
• But modern compilers are better at dealing with
  modern processors
• More lines of code ? more errors and less
  productivity

96
Fallacies

• Backward compatibility ? instruction set doesnt
  change
• But they do accrete more instructions

x86 instruction set
97
Concluding Remarks

• Design principles
• 1. Simplicity favors regularity
• 2. Smaller is faster
• 3. Make the common case fast
• 4. Good design demands good compromises
• Layers of software/hardware
• Compiler, assembler, hardware
• MIPS typical of RISC ISAs
• c.f. x86

98
Concluding Remarks

• Measure MIPS instruction executions in benchmark
  programs
• Consider making the common case fast
• Consider compromises