Fred Burghardt, Alan Tsao,

1
PicoRadio Network Emulation on BEE

• Fred Burghardt, Alan Tsao,
• Mike Sheets, Tufan Karalar, Jan Rabaey

2
PicoRadio Network In Brief

• Properties
• system consisting of sensors (sources),
  monitors (controllers), and actuators (sinks),
  organized
• into local neighborhoods.
• Assumptions
• no or minimal infrastructure
• range of any node ltlt network size
• any node can act as repeater
• Optimization Goals
• Global energy
• System survivability

3
The Node
Clock
UI
Solar Cell
Regulators
Memory
Analog Baseband
Sensors
4
Digital Network Processor
Structural View
Logical View
16kB CODE
Sensor/actuator interface
App/UI
4kB XDATA
DW8051
256 DATA
Chip Supervisor
Transport
Aggregation/ forwarding
Serial
Interconnect network
Network
DLL(MAC)
SIF
FlashIF
Serial
Locationing
Chip Supervisor
ADC
DLL (MAC)
GPIO
SIF
LocalHW
PHY
ADC
Baseband
Channel
5
Core Verification Problem

• PicoRadio networks are
• Highly asynchronous
• Event driven
• Many orders of magnitude between events
• For example, the DLL
• Has 11 largely independent timers for things like
  timeouts, periodic events, etc.
• Timer values range from tenths of ms to seconds
  (5 OM).
• From system clock to slowest timer is 8 OM.
• Some actions depend on a sequence of events
  (packet Tx/Rx, timer expiration) e.g.
  initialization
• So, software simulation for operations beyond
  (simple) initialization becomes problematic

6
Our Solution BEE

• Advantages
• Network operates in real time, so dynamic
  behavior is more representative of a real
  network.
• Enables testing of networks of more than two
  nodes, where software simulation is not
  practical.
• Performance burden does not increase by adding
  nodes.
• Acquisitions can be repeated in minimal time.
• Disadvantages
• Long build time for FPGA images. BUT,
  simulations takes a long time to run, and vector
  definition is challenging.
• Potentially complex setup. BUT, this is only
  done once.
• Physical presence occasionally required in lab.
  BUT, only to change cables, a fairly rare event.

7
Simulation vs. BEE
8
Mapping a PicoRadio Network to BEE
Pico Node
Pico Node
Chan Model
Pico Node
Riser Cards
Riser Cards
Pico Node
Pico Node
Chan Model
Pico Node
9
Programming the Channel Model

• Crossbar FPGAs are programmed with a channel
  model including
• Interconnect table
• Bit error generator
• Full connectivity between FPGAs in matrix can be
  achieved

• The Crossbars are controlled from a workstation
  via the Charm Monitor GUI written by Allen Tsao,
  which uses ethernet to talk to a StrongARM on the
  BEE, which in turn programs the crossbars.

10
Extracting Information From BEE

• Single-ended signals mapped directly
• FPGA I/O pin ltlt gtgt riser card ltlt gtgt logic
  analyzer probe.
• Logic Analyzer Parameters
• 128 channels
• 4M sample per channel memory
• 2.5ns minimum sampling resolution (async)
• Example Sample rate of 20ns yields a capture
  window of 80ms
• Standard riser card pin ltlt gtgt channel mapping so
  that analyzer pods are interchangeable

11
Data Representation

• Activity represented as signals or buses on a
  timing diagram.
• Can simultaneously view
• State of DLL state machines
• Critical intra-chip interfaces
• Activity on Tx and Rx for multiple nodes.

Neighbor List / DLL Interface detail
Successful data transfer
12
Primary Tools
VHDL Generation
Insecta Subset
Postprocessing
Custom Scripts
VHDL Compilation
Certify
Xilinx ISE
Xilinx Bitfile Generation
13
Conclusions

• Simulation is appropriate up to a point
• Sub-block and interface behavior verification.
• Reaches limit with 2 copies of DLL, for instance.
  After that, sim time and vector definition
  become unmanageable.

• BEE is essential for meaningful multi-node,
• multi-neighborhood tests
• Nodes create their own vectors.
• No performance penalty for additional nodes.
• Small incremental increase in build time for
  additional nodes.
• Problem becomes interpretation of results where
  to look given limited acquisition window.
• Can use higher level debug e.g. printfs to
  console from nodes.