TRD electronics Production and Testing

1
TRD electronicsProduction and Testing

• Wim de Boer, Chan Hoon Chung, Florian Hauler,
• Mike Schmanau, Andreas Sabellek, Georg Schwering
• IEKP - Universität Karlsruhe (TH)
• RWTH-Aachen I

2
Outline

• DC/DC Converter Testing
• UDR2 ADC timing issue, production status, plans
  for testing
• S9011AUv2, UPSFE production status, plans for
  testing
• UPD-Box final layout with terminal block
  fixture, production schedule for terminal block
  fixture, plans for FM/FS assembly
• Summary

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TRD(U)-Electronics Overviewafter weight reduction
Ucrate TRD electronic crate UBP TRD
backplane UPD TRD power distribution box
V2
V2
UPSFE TRD power supply for front end UDR TRD
data reduction board JINF data concentrator and
link to higher DAQ for TRD UHVG TRD high
voltage generator UFE TRD front end UTE TRD
tube end UHVD TRD high voltage distributor
removed USCM USCM functionality covered partly by
JINFV2
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DC/DC converter testing (M.Schmanau)

• Procedure 1. Functional test ON/OFF Signals
  Failure Status above maximum load
  Efficiency curve measurement 2. Thermal cycling
  with tests at max. and min. operational
  temperature Functional test ON/OFF Signals
• Failure Status above maximum load
  Efficiency measurement at nominal load
• Results for TRD related converters
• S9053U no problems
• S9048 one coil on all converters was not
  properly assembled, assembly note was partly
  wrong
• S9056 faulty temperature sensor

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DC/DC converter testing II

• Problem One S9048 PCB was damaged during
  testing What to do?
• Option A Reproduce one PCB. Unfortunately there
  are not enough components to assemble one
  more S9048. A critical component is the
  coil. Originally 21 were procured for FM/FS. 2
  coils appeared to be damaged during
  production. This option allows us to have
  one fully wired UPD Flight-Spare!!
• Option B Do not reproduce one more S9048. This
  option does not allow to have one fully wired
  UPD Flight-Spare!!My preference is option A.

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QM2 U-Crate
6 UHVG
JINFv2
3 UPSFEv2
6 UDR2
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UDR2 Status I
TRD Frontend Simulator In order to simulate
the frontends during ESS and TVT, a frontend
simulator was used. This device simulates the
load to the USPFE-boards and answers the signals
of the UDR2-boards to recognize any faults.
Load resistors
UPSFE
Heat Interface
Power for front ends
Load resistors
DAC level
DAC
ADC
control signals
UDR2
UFS
Clock ADC
FPGA/DSP
LVDS
digitized DAC level
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UDR2 Status II

• And indeed problem was discovered during ESS
  Normal output at 55C (left), Anomaly at -25C
  (right). Problem could be traced back to cabling
  length. Here we used slightly shorter cabling
  than nominal. It shows that timing gets modified
  with temperature. For TVT we used extended
  cabling. Problem does not show up any more.But
  Since TRD cable lengthes were reduced recently,
  the Actel firmware had to be retuned and again
  tested.

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UDR2 Status III

• UDR2 Actel firmware was retuned last week at CERN
  by VK and tested in thermal vacuum chamber
  between -25C and 60C by FH.
• It was not possible to cause the ADC signals
  running out of sync again even with additional
  cabling length of /- 0.5 m to maximum and
  minimum cabling. Maximum and minimum allowable
  voltages (3,1V to 3,45), which could influence
  Actel internal timing, were considered as well.
• Since no problems were spotted, 30 Actels were
  burnt last week at CERN and brought to Taipei for
  UDR2 assembly.
• PCB production was expected to be finished next
  week.
• It is expected that 15 UDR2 PCA will be finished
  beginning of August latest, allowing the testing
  to be started on August 7th.
• FM/FS Frontpanel production go ahead was given
  May 17th.
• Frontpanels have to be mounted to allow the tests
  being started.

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UPSFEv2, S9011

• UPSFE
• UPSFEv2 FM/FS production go ahead has been given
  in March
• 9 UPSFEv2 FM/FS PCB and PCA are finished.
• Frontpanel production go ahead was given on May
  17th.
• S9011AUv2/S9011B
• S9011AUv2 PCB finished on June 8th. PCA should
  be ready by August 7th.
• S9011B PCB finished on June 17th. PCA should be
  ready by a date defined by Giovanni (August).
• Testing
• UPSFE, S9011AUv2 will be tested in a common
  effort together with the UDR2 boards on August
  7th. Is this ok for CSIST?
• We suggest that S9011Bs are tested by Tracker
  people again. This procedure was already
  performed during QM2 production.

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old QM2 UPD-Box
Slow control connection to U-Crate
Power supply connectors for U-Crate and 28V
4 bus bars (double redundancy)
Disadvantage of bus bar solution Conductive 28V
bus bars are not protected against possible
shorts by floaters
S9011AUv2control electronics
S9011B Filter
S9056 120V/5V
S9056 120V/5V
S9056 120V/5V
S9048 /- 2.8V
S9048 /- 2.8V
S9048 /- 2.8V
S9053U 3.3V
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intermediate QM2 UPD-Box
Bus bars are replaced by Terminal Blocks or
Terminal Junction Modules Series I M81714
4 Terminal Blocks
However, there is no convenient way to properly
fix the terminal blocks to the I-Frames. gt
custom fixture had to be developped.
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new QM2 UPD-Box
KA Terminal Junction Block Fixture

• Advantages
• common solution for every xPD Box with 4
  terminal blocks since it is simply screwed on one
  single I-Frame and it does not depend on the
  I-Frame spacing in the box.
• Simple design can be easily machined.

1 mm clip to hold terminal blocks
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Terminal Fixture production

• Production was started mid of June. 30 terminal
  block fixtures without helicoils will be finished
  mid of September.
• CSIST was asked to take over the surface
  treatment and they accepted.
• After surface treatment, helicoils will be
  inserted at University of Karlsruhe
  (alternatively at CSIST)
• UPD-Box will be assembled as soon as Mil-spec
  connector procurement is finished.

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Plans for UPD Assembly

• UPD Assembly document is close to be finished.
  How will we proceed for the assembly?
• Since cable soldering on the DC/DC converters and
  S9011 is a delicate business which requires space
  qualified soldering skills, it is suggested that
  CSIST performs the cable soldering and the
  assembly with our support.
• Assembly can be started as soon as connector
  procurement is finished. Mikes estimation is
  end of September/beginning of October.
• For the first UPD, one person from Karlsruhe will
  be at CSIST. Has the document to be translated?

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Summary

• DC/DC converter FM/FS production finished. All
  TRD converters available, except of one S9048.
• UPSFEv2/S9011 board production is finished. UDR2
  board production is expected to be finished end
  of July.
• Terminal block fixture production w/o surface
  treatment will be finished mid of September.
• CSIST agreed on taking over the surface treatment
  for the terminal block fixtures.
• Board level testing should take place August 7th.
• XPD assembly is suggested to be performed with
  the help of CSIST. Most likely beginning of
  October.