Implementing a Cache Controller using Content Addressable Memory

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Implementing a Cache Controller using Content
Addressable Memory

• Rupa Balan

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Block Diagram of cache controller
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Content Addressable Memory Introduction

• CAM is designed to enhance data retrieval speed
  from a particular location in a storage array.
  Instead of using an address to read the data,
  such as a RAM, the data is supplied as an input
  to locate the address. CAM determines if the data
  is found within a storage array. When a match is
  found, the responder bit associated with the
  corresponding memory word is set. A basic CAM
  element consists of input data, a storage
  location, and a comparator.

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CAM Modes

• Single Match Mode
• Multiple Match Mode
• Ternary CAM mode

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16 X 8 CAM
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Block Diagram of the 2 cache Directories
Implemented using CAM
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Cache Controller Modes

• VHDL code and simulation scripts have been
  written for the following cache controller modes
• CACHE HIT ON MEMORY READ
• CACHE MISS ON MEMORY READ (THEN CACHE WRITE)
• CACHE WRITE FROM PROCESSOR (WRITTEN TO PROCESSOR
  IMMEDIATELY
• CACHE ERASE (CACHE INVALIDATE)