Task II Physical Design Tools

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Task II - Physical Design Tools
Task Leader Simon Wong, Stanford Principal
Investigators Stanford Robert Dutton, Giovanni
De Micheli (DT FC) MIT Jacob
White RPI Yannick Le Coz Summary
Statement Creation of a new frontier library of
3-D interconnect cells that can be combined
to generate accurate models and expedite the
synthesis of interconnect networks operating at
multi-GHz clock frequencies.
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Challenges

• Drastic increase in interconnect network
  complexity, material options and operating
  frequency.
• Interconnect structures (line, corner, via) are
  more variant than devices (typically, only width
  is varied).
• High frequency effects need to be accounted for.
• Coupling effects, especially long range ones
  (e.g., inductive) are difficult to model.
• Lead to long design cycle and high cost.

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Objectives
Approaches

• Develop accurate interconnect analysis tools
• Enable the creation of a library of optimized
  interconnect cells for synthesis.
• Develop approaches for handling massively coupled
  problems

• A hierarchy of physical design tools for
• generation of 3-D interconnect structures,
• high frequency electromagnetic analysis of 3-D
  structures, and
• generation of approximate circuit models.
• Integrate the physical design tools with a new
  breed of test structures and extraction
  methodology .
• Substrate coupling, thermal analysis

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Accurate Generation/Abstraction of 3-D
Interconnect Structures Prof. R. Dutton,
Stanford University

• Objective
• Modeling capabilities to systematically
• capture physical details of interconnects
• abstract features supporting performance
  modeling.
• Approach
• Geometry modeling and associated detailed
  structures derived from layout and abstracted
  process simulation (Task VI) will support a
  hierarchy of simulation and modeling tools
• materials dependencies (i.e. stress, grains...)
• meshed as well as lumped modeling tools
• Milestones
• define abstraction approach for heterogeneous
  data (i.e. layout TCAD materials properties)

• Milestones (contd)
• demonstrate hierarchical abstract of geometry
  across multi-domain structures
• develop new algorithms that maintain physical
  links with reduced-order models
• verify accuracy and applicability (Task I) based
  on test structures and circuits

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Automatic Generation of Accurate Circuit Models
Prof. J. White, MIT Prof. R. Dutton, Stanford

• MILESTONES
• Wavelet and Precorrected-FFT Acceleration plus
  MOR
• Accelerated Substrate Noise
• Accelerated E-M Noise

• OBJECTIVE
• 3-D Structure Circuit Model
• Valid to 100GHZ
• Analyze Massively Coupled Problems
• Substrate Noise, E-M Noise, EMC
• APPROACH
• Multigrid and Wavelet and Precorrected-FFT based
  Sparsification
• Novel Integral Formulations
• Near-Optimal Model-Order Reduction

Full Chip Interconnect
Sparse Circuit Representation
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Library of Optimized Interconnect CellsProf. S.
Wong, Stanford University

• MILESTONES
• High frequency properties of advanced
  interconnect materials
• Library of optimized interconnect cells

• OBJECTIVE
• Develop a library of optimized interconnect
  cells that are appropriate for synthesis.
• APPROACH
• Heavy utilization of the hierarchy of analysis
  tools developed in this task.
• Experimental Characterization of advanced
  interconnect materials.
• Incorporation of innovative signal engineering
  (e.g., from Task I and DT FC).

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A Multi-Scale Floating Random-Walk Algorithm for
Thermal Analysis of Complex IC-Interconnect
Structures Prof. Yannick L. Le Coz, Rensselaer
Polytechnic Institute
OBJECTIVE Development of an efficient,
multi-scale floating random-walk interface for
the commercial IC-interconnect CAD tool
QuickCapTM. Our application is local thermal
analysis of complex, multilevel IC-interconnect
and transistor structures. APPROACH The complex
matrix of interconnect metal, ILD, and
transistors will be accurately represented over a
3D local domain of interest. Global
material-property averaging techniques will be
developed to describe exterior regions. The
QuickCap capacitance extractor will then be used
to evaluate a thermal-capacitance matrix,
which, upon inversion will yield local
temperatures.

• MILESTONES (contd.)
• Verify computational accuracy by means of direct
  comparison with brute-force local solution.
• Examine parallel-processing techniques to
  ac-celerate solution convergence (should
  additional NYS support become available).

• MILESTONES
• Establish matrix-inversion procedures for
  QuickCap capacitance data.
• Define multi-scale material-property averaging
  tech-niques for global, exterior representation.

Example 3D Floating Random Walk
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Comparison of Device and Interconnect Modeling
Strategies
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Interfaces between Focus Centers
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Collaborations Between Focus Centers

• Interface at the circuit component level
• Generate library of optimized interconnect cells
  that are appropriate for synthesis
  (floorplanning)
• Reduce design cycle
• Stanford and MIT are involved in both Centers
• Frequent meeting between the two Centers to
  ensure synergism, enhance collaborations and
  avoid duplication of efforts

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