A Low Power ContentAdaptive Texture Mapping Architecture for RealTime 3D Graphics

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A Low Power Content-Adaptive Texture Mapping
Architecture for Real-Time 3D Graphics

• Jeongseon Euh, Jeevan Chittamuru, and Wayne
  Burleson
• Department of Electrical and Computer Engineering
• University of Massachusetts Amherst
• jeuh, jchittam, burleson_at_ecs.umass.edu

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Outline

• Objective and Motivations
• Texture Mapping
• Human visual perception
• Content adaptive texture mapping
• Proposed architecture
• Results
• Conclusion

(From Quake II PC Game)
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Objective and Motivations

• Objective
• Propose a content adaptive approach to real-time
  3D graphics texture mapping for saving power
• Motivations
• Increasing computation cycles
• Virtual reality
• 3D game
• 3D operating system
• 3D graphics for post-PC computing
• Wearable computer
• Notebook computer
• Heads-up display
• Cockpit information center

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Texture Mapping

• Texture mapping To give realism with less effort
• Interpolation To reduce aliasing
• Point Sampling
• Bilinear 4 Texels
• Trilinear 8 Texels (Mip-mapping)
• Computation Intensive Up to 60 of Fragment
  Generator (Trilinear)
• High memory bandwidth 100

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Texture Mapping

• Computation intensive (per fragment)

• High memory bandwidth
• 640x480 display, 30 Hz frame rate, 1 layer full
  screen texturing

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Texture Mapping

• Bilinear interpolation Trilinear
  interpolation

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Human Visual Perception

• Visual sensitivity varies with spatial freq.
  (image complexity) and temporal freq (motion).
• Used to reduce the number of computations for
  video coding and 3D graphics
• 3D graphics Level of Detail, Perceptually-based
  rendering, etc.

• Spatiotemporal Contrast Sensitivity Function (D.
  Kelly 79)

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Content Adaptive Texture Mapping

• Adaptive algorithm
• Bilinear or Trilinear interpolation
• Computation and memory access control
• Computation speed control
• Dynamic voltage scaling (DVS)
• Clock speed 100MHz Clk for Trilinear, 50MHz Clk
  Bilinear
• Supply voltage 2.5V for Trilinear, 1.6V for
  Bilinear
• System level supply or On-chip circuitry

• Control criteria
• Contrast sensitivity function
• Predefined spatial frequency of texture map
• Object speed

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Proposed Architecture
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Content Adaptive Texture Mapping

• Experimental configuration (TSMC 0.25? CMOS)
• Adaptive texture mapping mode 1
• Trilinear interpolation
• Clock speed 100 MHz
• Supply voltage 2.5 V
• Adaptive texture mapping mode 2
• Bilinear interpolation
• Clock speed 50 MHz
• Supply voltage 1.6 V
• To have the same throughput, use both
  interpolation pipelines for both modes
• Application software Quake II PC game

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Simulation Results

• 640x480 display, 10 frames
• Power savings from reduced computation

• Memory access pattern

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DVS Scheme Implementation

• Feasibility of using DVS and switching overhead

Based on 10 frames of Quake II Switching
delay ? 100?s

• With about 35 switches, DVS can be used for 92
  100 of the bilinear computation
• Switching overhead is less than 2

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Conclusion

• New approach Content adaptive H/W for low power
  3D graphics texture mapping
• Human visual perception exploited to reduce
  texture mapping computation
• Adaptive texture interpolation and DVS scheme
• ? up to 73.8 power savings from computing unit,
• up to 33.9 less memory accesses
• Constraints
• Control parameters from other stage of 3D
  graphics rendering system
• Trade off between image quality and power savings
  ratio

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