A Pulsar Digital Filter Bank for Parkes

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A Pulsar Digital Filter Bankfor Parkes

• Dr. Grant Hampson
• ATNF Research Engineer
• 5 February 2007

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Pulsar Digital Filter Bank (PDFB) User
Requirements

• Pulsar DFB minimum requirements
• ADC 9-bit sampling
• 1GHz of output bandwidth
• Dual polarisation
• 2048 frequency channels
• 2048 pulsar phase bins
• 4-product correlator
• 4ms minimum pulsar period(for this
  product-channel-bin combination)
• There are many other modes to the PDFB system
  including a Raw DataCapture, Spectrometer, and
  PulsarSearch mode.

4ms
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PDFB System Design

• The PDFB system is designed using components from
  CABB(Compact Array Broadband Backend upgrade)
• Dual ADC designed for CABB developments
• Signal processing using CABB DSP board
• All components contained in a single 3U-19rack
  unit 500mm deep

Gain
Mode
Digital Filter Bank
Four Product Correlator
Dual ADC 9-bit 2GSPS
Computer System
Raw Data Capture Spectrometer Pulsar
Search Pulsar Folded
DDR2 Memory
Pol.A
Pol.B
5MHz
Synthesizers
Pulsar Timing Unit
1pps
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Frequency Synthesizers

• There are three frequency synthesizers in the
  PDFB system
• Pulsar Timing Unit contains a 128MHz clock for
  timing of PTU signals(this is referenced to 5MHz
  and synchronized with the 1pps signal.)
• ADC/DFB Reference contains a synthesizer to
  generate 32MHz from the 5MHz reference and
  synchronized with the 1pps signal.
• ADC/DFB contains two synthesizers which use the
  32MHz reference to generate the ADC sampling
  clock of 2.048GHz, and the processing clock of
  the DFB, equal to 256MHz. Data serializes use a
  640MHz reference.

5MHz
PTU Signals (Bank, Period, Bin, calibrator, etc.)
1pps
Div 32
256MHz
2.048GHz
Dual Synthesizer
640MHz
32MHz Synthesizer
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Dual 2GSPS ADCs
Intel 10Gbps Serialiser
Atmel ADC and Dmux
Power

• CABB ADC board
• 45dB SFDR
• ADCs treated independently

IFinputs
Four10Gbpsstreams
ADC with Synthesizer in enclosures
Synthesizer Inputs(2048, 640, 32 MHz)
Xilinx SX35 FPGA
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Pulsar DFB/PPU Processing Engine

• The signal processing engine of the Pulsar
  DFB system is the CABB DSP board
• 4 - Xilinx SX55-11 FPGAs(half for DFB, half for
  PPU)
• 4 DDR2 266MHz memories(attached to PPU)
• SOM with PCI 32-bit/66MHz
• FPGAs processdata at 256MHz
• Rockets for data comms
• 10Gb Ethernet
• Between boards for RFI
• Connects to RTM which connects to ADC board

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Why DDR2 Memory?

• The key to success in the pulsar processing unit
  is the memory BW required to achieve the folded
  data mode processing requirements (not quantity!)
• The memory bandwidth required can be calculated
  usingProcessing rate x integration size x
  parallel data paths x simultaneous R/W? 256MHz x
  32-bit x 16 x 2 32Gbytes/second!
  (or
  256Gbits/second!!)
• DRAM is large, cheap, low power and in modules,
  large controller(QDR is small, expensive, high
  power, no modules, no controller)
• Low profile to fit ATCA slot width (VLP MiniDimm)
• DDR controller provided by Xilinxis basis for
  our controller(dual clock support 256/266)

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Matlab, Simulink and Xilinx System Generator

• Matlab is a powerful text based simulation tool
• Simulink is a powerful graphical based simulation
  tool
• The combination makes it the ultimate simulation
  tool(Matlab generates stimulus ? Simulink ?
  Matlab analyzes results)
• Xilinx System Generator converts the Simulink
  Models to VHDL code
• VHDL wrappers connect the VHDL model to the
  physical IO interfaces(e.g. DDR, clocks, DCMs,
  constraints, etc.)
• The VHDL is compiled using Xilinx ISE8.2 to
  produce FPGA bitfiles

VHDL Wrapper
MatlabStimulus Analysis
SimulinkModels
VHDL SimulinkModel
Xilinx VHDL Synthesis
Bitfile Programs FPGAs
Xilinx SystemGenerator
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Digital Filter Bank Configurations

• The Digital Filter Bank (DFB) input is real ADC
  samples
• The DFB processes them into a number of frequency
  channels using a polyphase filtering method
  (critically sampled DFB)
• There are two distinct parts to the DFBa
  filtering stage (FIR) followed by a frequency
  transform (FFT)
• Depending on the bandwidth of the input data it
  becomes feasible to separate the data over
  several data paths which gives rise to the
  radix of the design.
• In order to process 1GHz of BW (2GSPS real) this
  is dividedover 8 data buses (a Radix-8 design)
  each operating at 256MHz.
• Fully custom Radix-2, Radix-4, Radix-8 DFBs
  have been developed for BWs of 256, 512,
  1024MHz.
• As the BW reduces the Radix of the design
  decreases and at BWs below 256MHz it is
  possible to use the Xilinx FFT

ADCs
FIRPart
FFT Part
PPU Part
Pol.A
Radix-R
Radix-R
Radix-R
Pol.B
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Digital Filter Bank Sizes

• Radix-4 DFB filter bank synthesis results
• Separate FIR and FFT parts can see resources
  vs. length

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Pulsar Processing Unit (PPU) Modes

• There are four fundamental modes in the PPU
• Raw Data Capture of ADC samples and DFB output
  (parameters BW, number of samples)
• Spectrometer (parameters BW, products, channels,
  bits)
• Pulsar Search Mode (parameters BW, products,
  channels, bits, integration time)
• Pulsar Folded Mode (parameters BW, products,
  channels, bins, bits)
• Each of these modes is customizable to suit the
  user application.
• The PPU processes many parallel data streams
  simultaneously (Radix-R)

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Pulsar Folded Mode

• The Pulsar Folded Mode is the main mode of the
  PDFB
• The PTU generates timing signals at the pulsar
  frequency (or period)
• Each pulsar period can be divided into many
  phase-bins
• Depending on the BW of the input data and the
  number of DFB frequency channels the data can be
  folded at a particular rate
• By modifying the BW and/or frequency-channels
  and/or phase-binsit is possible to change the
  folding rate.

Approximate Minimum Pulsar Period (in ms)for a
1024MHz BW, 4-product PSRDFB(yellow is proposed,
gray not possible with this BW)

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Conclusions

• The Pulsar Digital Filter Bank System is a fully
  integrated solution
• As much flexibility as possible has been designed
  into the system.
• PDFB based on the CABB ADC and DSP hardware
• The heart of the PDFB is four programmable
  FPGAsthat can deliver a multitude of processing
  configurations
• All hardware exists in system awaiting
  installation at Parkes
• Still lots of work to do Multiple pulsars, RFI,
  etc.
• See parts of the hardware in the demonstration!

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Thank You

• ATNF / Electronics Group
• Name Grant Hampson
• Title Research Engineer
• Phone (eg. 61 3 9372 4647)
• Email grant.hampson_at_csiro.au
• Web www.atnf.csiro.au

Contact CSIRO Phone [phone] 9545
2176 Email enquiries_at_csiro.au Web www.csiro.au