H05H0 Project Overview

1
H05H0 Project Overview
slides available onwww.esat.kuleuven.be/yvanderp
/jpeg.html
2
From Specification to Implementation
2 Exercice Sessions
3
From Specification to Implementation
Part 1
4
From Specification to Implementation
Part 2
GEZEL
5
From Specification to Implementation
Part 3
GEZEL
FPGA
6
Organization

• Exercice Sessions, Part 1
• system design teams
• short assignments
• Part 2, 3
• implementation teams (2-3 students)
• interface documents
• project presentation
• project report

7
Schedule 2008
HW design spec.
Sections ready
Fx-Pt Code Report
Report Slides
System ready
Synthesis Done
Drink
8
From the dataflow model to implementation (GEZEL)
Max. rate UXGA_at_15fps
JPEG Encoder
b5
RGB
b1
b2
b3
rgbyuv
dct
camif
T1
T4
T2
Trgbyuv
Tdct
Tcamif
Main FSM
b4
b6
quant
huf
fdump
T1
T1
T3
T4
Tquant
Thuf
b3
JPEG
9
From the dataflow model to implementation (GEZEL)
GROUP A
Max. rate UXGA_at_15fps
JPEG Encoder
b5
RGB
Ying He HongXu Zhao
Maarten Tytgat Georges Nédée
Vladimir Rozic Domonkos Gergelyi
b1
b2
b3
rgbyuv
dct
camif
FxP
Trgbyuv
Tdct
Tcamif
Main FSM
Ying He HongXu Zhao
b4
b6
quant
huf
fdump
Vladimir Rozic Domonkos Gergelyi
Vladimir Rozic Domonkos Gergelyi
Bart Marien Gitte Vanwinckelen
Tquant
Thuf
b3
JPEG
9
10
From the dataflow model to implementation (GEZEL)
GROUP B
FxP
Max. rate UXGA_at_15fps
JPEG Encoder
b5
RGB
Junjie Ren Leo Nwofa
YuFei Liu ShiQi Li
Thomas Raes Wouter Volkaerts
b1
b2
b3
rgbyuv
dct
camif
Trgbyuv
Tdct
Tcamif
Main FSM
Junjie Ren Leo Nwofa
YuFei Liu ShiQi Li
b4
b6
Junjie Ren Leo Nwofa
quant
huf
fdump
Hans Meyvaert Klaas De Craemer
Tquant
Thuf
b3
JPEG
10