Mthodologie de Conception de Systme pour Architectures Parallles

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A refinement methodology andarchitecture
evaluation using an SDR example
Presented by Primrose Mbanefo Supervised
by Ilia Oussorov, CPR ST, Infineon Technologies,
AG. Pierre Wodey, ISIMA, Clermont-Ferrand.
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PLAN

• Introduction
• The methodologie
• The refinement proposition
• Validating the refinement
• UMTS
• SIMD
• The refinement process
• The refinement
• Functional level
• DPCE
• Transactionnal level
• Conclusion

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Introduction

• UMTS
• Parallel architecture
• SystemC methodology
• SystemC
• A system level design language

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System Level Design

• Objective
• Unification of the developpement of hardware and
  software

A system
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The proposed refinement

• Hardware and software introduction

System conception
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SDR

• SDR Software Defined Radio
• Software controlled characteristics
• Modulation techniques, security functions,
  frequency ...
• Uses simpler hardware platforms

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Technical generations

• 1st generation
• Early 80s
• First analog cellular systems

• 2nd generation
• Early 90s
• First digital cellular system
• 2.5 generation
• Late 90s
• Enhanced 2g systems data rates are up to 144kbs
• SMS, Pictures

• 3rd generation
• concerns TODAY!
• data rates should go up to 2Mbs
• Multimedia, Internet, Broadband

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UMTS Network

• UMTS Universal Mobile Telecommunication System
• European 3G system

UMTS Network
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Cells
Cells

• Intercell-Interferences
• Echos

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CDMA

• Synchronising to a base station
• CDMA technique is used for this
• CDMA Code Division Multiple Access
• as opposed to
• FDMA - Frequency DMA
• TDMA - Time DMA

F/T/C-DMA
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UMTS data

• Data format
• Frames
• Slots
• Chips
• complex numbers

A frame of data
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Codes for synchronisation to the base station

• Primary synchronisation code
• The same for all base stations
• completely orthogonal
• Aids in slot detection

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group 3
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Codes for synchronisation to the base station

• The third and last code for synchronisation
• The primary scrambling code
• There are 512 primary scrambling codes divided
  into 64 groups of 8 codes
• Each base station uses one of the codes in the
  group used in the secondary synchronisation code
• Example

Base station is identified with primary
scrambling code 5 of group 3
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Synchronisation channels

• The synchronisation codes are transported by
  three channels
• The Primary Synchronisation CHannel (P-SCH)
• The Secondary Synchronisation CHannel (S-SCH)
• The Common PIlot CHannel (CPICH)

Cell search channels and codes
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Initial cell search

• Initial cell search Search for the strongest
  base station signal effectuated by the users
  equipment (mobile phone, pda, laptop) on start-up
• Made up of the three synchronisations
• Primary synchronisation
• The UE knows where the start of slot of the
  strongest BS is found
• Secondary synchronisation
• The UE knows where the start of frame of this BS
  is found
• It also knows which code group it belongs to
• Primary scrambling code search
• The UE knows exactly which data is coming from
  the BS

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Initial cell search

• Cell search is known to be time consuming because
  of the numerous computations to be done
• Detect its critical points
• Evaluate a target architecture based on SIMD cores

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SIMD
Shared Memory
Parameters

• Local memory size
• Memory bus widths

• Number of PEs
• Number of registers

SIMD core architecture
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The refinement process

• Usual

Classical refinement process
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The refinement process

• Proposed

The refinement to be validated
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Functional level

• Aims
• Understand the application
• Give a preliminary evaluation of the architecture
• First obstacle
• The communication channel
• 3 levels of data representation
• Make the 3 levels co-exist

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Data parallelism extraction

• SystemC has no way of expressing data parallelism
• DPCE Data Parallel C extension
• Translating from SystemC to DPCE
• rather straight forward
• SystemC modules become DPCE files
• Procedures and functions will be in their
  respective files
• Data structures become DPCE shapes
• e.g frame class becomes a shape
• Programmer should bear in mind that this is data
  parallel code
• Where possible use the parallel operators on
  parallel objects

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Entire model representation

• Model used by the two levels

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SIMD
Shared Memory
Parameters

• Local memory size
• Memory bus widths

• Number of PEs
• Number of registers

SIMD core architecture
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Conclusion

• Two versions of the Untimed Functional Level
  exist
• It takes 4 weeks to write it the first time to
  get a good understanding
• Two versions of the Timed Functional Level exist
• It takes about two weeks to refine it once a
  refinement direction has been chosen
• Working on the TLM